EX64-FTQG100PP datasheet, PDF - EEWORLD Datasheet

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EX64-FTQG100PP: DescriptionFPGA, 256 CLBS, 6000 GATES, 250 MHz, PQFP100; Categorysemiconductor Programmable logic devices; File Size362KB，49 Pages; ManufacturerActel; Websitehttp://www.actel.com/

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EX64-FTQG100PP Overview

FPGA, 256 CLBS, 6000 GATES, 250 MHz, PQFP100

EX64-FTQG100PP Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	100
Maximum operating temperature	125 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	2.7 V
Minimum supply/operating voltage	2.3 V
Rated supply voltage	2.5 V
Processing package description	0.50 MM PITCH, PLASTIC, TQFP-100
state	ACTIVE
Craftsmanship	CMOS
packaging shape	SQUARE
Package Size	FLATPACK, LOW PROFILE, FINE PITCH
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	0.5000 mm
terminal coating	TIN LEAD
Terminal location	QUAD
Packaging Materials	PLASTIC/EPOXY
Temperature level	AUTOMOTIVE
organize	256 CLBS, 6000 GATES
Maximum FCLK clock frequency	250 MHz
Number of configurable logic modules	256
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Number of equivalent gate circuits	6000
The maximum delay of a CLB module	1 ns

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v4.3

eX Family FPGAs

FuseLock

Leading Edge Performance

•

240 MHz System Performance

350 MHz Internal Performance

3.9 ns Clock-to-Out (Pad-to-Pad)

•

Specifications

•

3,000 to 12,000 Available System Gates

Maximum 512 Flip-Flops (Using CC Macros)

0.22µm CMOS Process Technology

Up to 132 User-Programmable I/O Pins

•

Features

•

High-Performance, Low-Power Antifuse FPGA

LP/Sleep Mode for Additional Power Savings

Advanced Small-Footprint Packages

Hot-Swap Compliant I/Os

Single-Chip Solution

Nonvolatile

Live on Power-Up

No Power-Up/Down Sequence Required for Supply

Voltages

Configurable Weak-Resistor Pull-Up or Pull-Down

for Tristated Outputs during Power-Up

Individual Output Slew Rate Control

2.5 V, 3.3 V, and 5.0 V Mixed-Voltage Operation

with 5.0V Input Tolerance and 5.0V Drive Strength

Software Design Support with Actel Designer and

Libero™ Integrated Design Environment (IDE)

Tools

Up to 100% Resource Utilization with 100% Pin

Locking

Deterministic Timing

Unique In-System Diagnostic and Verification

Capability with Silicon Explorer II

Boundary Scan Testing in Compliance with IEEE

Standard 1149.1 (JTAG)

Fuselock™ Secure Programming Technology

Prevents Reverse Engineering and Design Theft

Product Profile

Device

Capacity

System Gates

Typical Gates

Dedicated Flip-Flops

Maximum Flip-Flops

Combinatorial Cells

Maximum User I/Os

Global Clocks

Hardwired

Routed

Speed Grades

Temperature Grades*

Package

(by pin count)

TQFP

CSP

eX64

3,000

2,000

128

–F, Std, –P

C, I, A

64, 100

49, 128

eX128

6,000

4,000

128

256

100

–F, Std, –P

C, I, A

64, 100

49, 128

eX256

12,000

8,000

256

512

132

–F, Std, –P

C, I, A

100

128, 180

Note:

*Refer to the

eX Automotive Family FPGAs

datasheet for details on automotive temperature offerings.

June 2006

eX Family FPGAs

Table of Contents

eX Family FPGAs

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

eX Family Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

2.5V/3.3V/5.0V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13

2.5V LVCMOS2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14

3.3V LVTTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15

5.0V TTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17

Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17

eX Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18

Output Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19

AC Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19

Input Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20

C-Cell Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20

Cell Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20

Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21

Temperature and Voltage Derating Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21

eX Family Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26

Package Pin Assignments

64-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

100-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

49-Pin CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

128-Pin CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

180-Pin CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

Export Administration Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

v4.3

iii

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