EX64-PTQ49 datasheet, PDF - EEWORLD Datasheet

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EX64-PTQ49: DescriptionFPGA, 256 CLBS, 6000 GATES, 178 MHz, PQFP100; Categorysemiconductor Programmable logic devices; File Size280KB，36 Pages; ManufacturerETC1

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EX64-PTQ49 Overview

FPGA, 256 CLBS, 6000 GATES, 178 MHz, PQFP100

EX64-PTQ49 Parametric

Parameter Name	Attribute value
Number of terminals	100
Minimum operating temperature	0.0 Cel
Maximum operating temperature	70 Cel
Processing package description	0.50 MM PITCH, PLASTIC, TQFP-100
each_compli	Yes
state	Active
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
clock_frequency_max	178 MHz
The maximum delay of a CLB module	1.4 ns
jesd_30_code	S-PQFP-G100
jesd_609_code	e0
moisture_sensitivity_level	3
Number of configurable logic modules	256
Number of equivalent gate circuits	6000
organize	256 CLBS, 6000 GATES
Packaging Materials	PLASTIC/EPOXY
ckage_code	LFQFP
packaging shape	SQUARE
Package Size	FLATPACK, LOW PROFILE, FINE PITCH
eak_reflow_temperature__cel_	225
seated_height_max	1.6 mm
Rated supply voltage	2.5 V
Minimum supply voltage	2.3 V
Maximum supply voltage	2.7 V
surface mount	YES
Craftsmanship	CMOS
Temperature level	COMMERCIAL
terminal coating	TIN LEAD
Terminal form	GULL WING
Terminal spacing	0.5000 mm
Terminal location	QUAD
ime_peak_reflow_temperature_max__s_	30
length	14 mm
width	14 mm
dditional_feature	ALSO REQUIRES 3.3V OR 5V SUPPLY

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v3.0

eX Family FPGAs

Le a di n g E d ge P er f o r m a n ce

• 240 MHz System Performance

• 3.9ns Clock-to-Out (Pad-to-Pad)

• 350 MHz Internal Performance

Sp e ci f i c a t i on s

• Individual Output Slew Rate Control

• 2.5V, 3.3V, and 5.0V Mixed Voltage Operation with 5.0V

Input Tolerance and 5.0V Drive Strength

• Software Design Support with Actel Designer Series and

Libero Tools

• Up to 100% Resource Utilization with 100% Pin Locking

• Deterministic Timing

• Unique In-System Diagnostic and Verification Capability

with Silicon Explorer II

• Boundary Scan Testing in Compliance with IEEE Standard

1149.1 (JTAG)

• Secure Programming Technology Prevents Reverse

Engineering and Design Theft

G en er al D e sc r i p t i on

• 3,000 to 12,000 Available System Gates

• As Many as 512 Maximum Flip-Flops (Using CC Macros)

• 0.22

CMOS Process Technology

• Up to 132 User-Programmable I/O Pins

Fe a t ur es

• High-Performance, Low-Power Antifuse FPGA

• LP/Sleep Mode for Additional Power Savings

• Advanced Small-footprint Packages

• Hot-Swap Compliant I/Os

• Single-Chip Solution

• Nonvolatile

• Live on power up

• Power-Up/Down Friendly (No Sequencing Required for

Supply Voltages)

• Configurable Weak-Resistor Pull-Up or Pull-Down for

Tristated Outputs during Power Up

eX P r o du ct Pr o f i l e

Device

Capacity

System Gates

Typical Gates

Combinatorial Cells

Maximum User I/Os

Speed Grades

Temperature Grades

Package

(by pin count)

TQFP

CSP

The eX family of FPGAs is a low-cost solution for low-power,

high-performance designs. The inherent low power

attributes of the antifuse technology, coupled with an

additional low static power mode, make these devices ideal

for power-sensitive applications. Fabricated with an

advanced 0.22

CMOS antifuse technology, these devices

achieve high performance with no power penalty

eX64

3,000

2,000

128

–F, Std, –P

C, I

64, 100

49, 128

eX128

6,000

4,000

128

256

100

–F, Std, –P

C, I

64, 100

49, 128

eX256

12,000

8,000

256

512

132

–F, Std, –P

C, I

100

128, 180

D e ce m b e r 2 0 0 1

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