Freescale Semiconductor, Inc.
MC56F8345/D
Rev. 8.0, 6/2004
56F8345
Preliminary Technical Data
56F8345 16-bit Hybrid Controller
• Up to 60 MIPS at 60MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• 128KB Program Flash
• Two Quadrature Decoders
• FlexCAN module
• Optional On-Chip Regulator
• Two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interface (SPIs)
• Up to four general-purpose Quad Timers
• Computer Operating Properly (COP)/Watchdog
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 49 GPIO lines
• 128-pin LQFP Package
RSTO
RESET
6
PWM Outputs
3
4
Current Sense Inputs
or GPIOC
Fault Inputs
Program Controller
and Hardware
Looping Unit
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• 4KB Program RAM
• 8KB Data Flash
• 8KB Data RAM
• 8KB Boot Flash
• Two 6-channel PWM modules
• Four 4-channel, 12-bit ADCs
• Temperature Sensor
V
PP
5
JTAG/
EOnCE
Port
V
CAP
4
OCR_DIS
V
DD
V
SS
7
5
Digital Reg
V
DDA
2
V
SSA
2
PWMA
Analog Reg
16-Bit
56800E Core
Low Voltage
Supervisor
Bit
Manipulation
Unit
6
PWM Outputs
3
4
4
4
5
4
4
Current Sense Inputs
or GPIOD
Fault Inputs
Address
Generation Unit
PWMB
Data ALU
16 x 16 + 36 -->36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
AD0
ADCA
AD1
VREF
PAB
PDB
CDBR
CDBW
Memory
Program Memory
64K x 16 Flash
2K x 16 RAM
4K x 16 Boot
Flash
Data Memory
4K x 16 Flash
4K x 16 RAM
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
R/W Control
AD0
ADCB
AD1
TEMP_SENSE
4
Quadrature
Decoder 0 or
Quad
Timer A or
GPIOC
Quadrature
Decoder 1 or
Quad
Timer B or
SP1I or
GPIOC
Quad Timer
C or GPIOE
Quad Timer
D or GPIOE
FlexCAN
System Bus
Control
External Bus
Interface Unit
*
External
Address Bus
Switch
6
5
A8-13 or GPIOA0-5
GPIOB0-4 or A16-20
*
External
Data
Bus Switch
4
D7-10 or GPIOF0-3
*
Bus
Control
6
GPIOD0-5 or CS2-7
4
IPBus Bridge (IPBB)
Peripheral
Device Selects
RW
Control
IPAB
IPWDB
IPRDB
2
Decoding
Peripherals
4
2
Clock
resets
P
System
O
Integration
R
Module
PLL
*
EMI not functional in
this package; use as
GPIO pins
SPI0 or
GPIOE
4
SCI1 or
GPIOD
2
SCI0 or
GPIOE
2
COP/
Interrupt
Watchdog Controller
Clock
O
S
Generator
C
CLKMODE
XTAL
EXTAL
IRQA IRQB
CLKO
56F8345 Block Diagram - 128 LQFP
© Motorola, Inc., 2004. All rights reserved.
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Document Revision History
Version History
Rev 1.0
Rev 2.0
Rev 3.0
Description of Change
Pre-Release version, Alpha customers only
Initial Public Release
Corrected typo in
Table 10-4,
Flash Endurance is 10,000 cycles.
Addressed additional grammar issues
Rev 4.0
Added “Typical Min” values to
Table 10-16
Editing grammar, spelling, consistency of language throughout family
Freescale Semiconductor, Inc...
Updated values in Current Consumption per Power Supply Pin,
Table 10-7,
Regulator
Parameters,
Table 10-9,
External Clock Operation Timing Requirements
Table 10-13,
SPI
Timing,
Table 10-17,
ADC Parameters,
Table 10-23,
and IO Loading Coefficients at 10MHz,
Table 10-24.
Rev 5.0
Added
Section 4.8 Factory Programmed Memory,
added the word “access” to FM Error Interrupt in
Table 4-5,
removed min and max numbers; clarified CSBAR 0 and CSBAR 1 reset values in
Table 4-10,
removed min and max numbers; only documenting Typ. numbers for LVI in
Table 10-6.
Updated numbers in
Table 10-7
and
Table 10-8
with more recent data,
Corrected typo in
Table 10-3
in Pd characteristics.
Replace any reference to Flash Interface Unit with Flash Memory Module, added note to
Vcap pin in
Table 2-3,
removed unneccessary notes in
Table 10-12;
corrected temperature
range in
Table 10-14;
added ADC calibration information to
Table 10-23;
and new graphs in
Figure 10-21.
Clarification to
Table 10-22,
corrected Digital Input Current Low (pull-up enabled)
numbers in
Table 10-5.
Removed text and Table 10-2; replaced with note to
Table 10-1.
Rev 6.0
Rev 7.0
Rev 8.0
2
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56F8345 Technical Data
Preliminary
Freescale Semiconductor, Inc.
56F8345 Data Sheet Table of Contents
Part 1: Overview . . . . . . . . . . . . . . . . . . . . 4
1.1. 56F8345 Features . . . . . . . . . . . . . . . . . . 4
1.2. 56F8345 Description . . . . . . . . . . . . . . . . 5
1.3. Award-Winning Development
Environment . . . . . . . . . . . . . . . 6
1.4. Architecture Block Diagram . . . . . . . . . . . 7
1.5. Product Documentation . . . . . . . . . . . . . 10
1.6. Data Sheet Conventions . . . . . . . . . . . . 11
Part 8: General Purpose Input/Output
(GPIO) . . . . . . . . . . . . . . . . . . . . . 114
8.1. Introduction . . . . . . . . . . . . . . . . . . . . . 114
8.2. Configuration . . . . . . . . . . . . . . . . . . . . 114
8.3. Memory Maps . . . . . . . . . . . . . . . . . . . 118
Part 9: Joint Test Action Group (JTAG) 118
9.1. 56F8345 Information . . . . . . . . . . . . . . 118
Part 2: Signal/Connection Descriptions 12
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . 12
2.2. 56F8345 Signal Pins . . . . . . . . . . . . . . . 14
Part 10: Specifications . . . . . . . . . . . . . 118
10.1. General Characteristics . . . . . . . . . . . 118
10.2. DC Electrical Characteristics . . . . . . . 122
10.3. Temperature Sense . . . . . . . . . . . . . . 125
10.4. AC Electrical Characteristics . . . . . . . 125
10.5. Flash Memory Characteristics . . . . . . 126
10.6. External Clock Operation Timing . . . . 127
10.7. Phase Locked Loop Timing . . . . . . . . 127
10.8. Crystal Oscillator Timing . . . . . . . . . . 128
10.9. Reset, Stop, Wait, Mode Select, and
Interrupt Timing . . . . . . . . . . . 128
10.10. Serial Peripheral Interface (SPI)
Timing . . . . . . . . . . . . . . . . . . 130
10.11. Quad Timer Timing . . . . . . . . . . . . . 133
10.12. Quadrature Decoder Timing . . . . . . . 133
10.13. Serial Communication Interface
(SCI) Timing . . . . . . . . . . . . . 134
10.14. Controller Area Network (CAN)
Timing . . . . . . . . . . . . . . . . . . 135
10.15. JTAG Timing . . . . . . . . . . . . . . . . . . 135
10.16. Analog-to-Digital Converter (ADC)
Parameters . . . . . . . . . . . . . . 137
10.17. Equivalent Circuit for ADC Inputs . . . 139
10.18. Power Consumptio . . . . . . . . . . . . n 139
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Part 3: On-Chip Clock Synthesis (OCCS) 29
3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . 29
3.2. External Clock Operation . . . . . . . . . . . 30
3.3. Registers . . . . . . . . . . . . . . . . . . . . . . . . 31
Part 4: Memory Map . . . . . . . . . . . . . . . . 32
4.1.
4.2.
4.3.
4.4.
4.5.
4.6.
4.7.
4.8.
Introduction . . . . . . . . . . . . . . . . . . . . . .
Program Map . . . . . . . . . . . . . . . . . . . .
Interrupt Vector Table . . . . . . . . . . . . . .
Data Map . . . . . . . . . . . . . . . . . . . . . . . .
Flash Memory Map . . . . . . . . . . . . . . . .
EOnCE Memory Map . . . . . . . . . . . . . .
Peripheral Memory Mapped Registers .
Factory Programmed Memory . . . . . . . .
32
33
34
38
38
40
41
65
Part 5: Interrupt Controller (ITCN) . . . . . 66
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
5.7.
Introduction . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . .
Operating Modes . . . . . . . . . . . . . . . . . .
Register Descriptions . . . . . . . . . . . . . .
Resets . . . . . . . . . . . . . . . . . . . . . . . . . .
66
66
66
68
68
69
93
Part 11: Packaging . . . . . . . . . . . . . . . . 141
11.1. Package and Pin-Out Information
56F8345 . . . . . . . . . . . . . . . . 141
Part 6: System Integration Module (SIM) 94
6.1.
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
6.8.
Introduction . . . . . . . . . . . . . . . . . . . . . . 94
Features . . . . . . . . . . . . . . . . . . . . . . . . 94
Operating Modes . . . . . . . . . . . . . . . . . . 95
Operating Mode Register . . . . . . . . . . . 95
Register Descriptions . . . . . . . . . . . . . . 96
Clock Generation Overview . . . . . . . . 109
Power-Down Modes Overview . . . . . . 109
Stop and Wait Mode Disable
Function . . . . . . . . . . . . . . . . 110
6.9. Resets . . . . . . . . . . . . . . . . . . . . . . . . . 110
Part 12: Design Considerations . . . . . . 144
12.1. Thermal Design Considerations . . . . . 144
12.2. Electrical Design Considerations . . . . 145
12.3. Power Distribution and I/O Ring
Implementation
146
Part 13: Ordering Information . . . . . . . 147
Part 7: Security Features . . . . . . . . . . . 111
7.1. Operation with Security Enabled . . . . . 111
7.2. Flash Access Blocking Mechanisms . . 111
Please see http://www.motorola.com/semiconductors for the most current Data Sheet revision.
56F8345 Technical Data
Preliminary
3
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Part 1 Overview
1.1 56F8345 Features
1.1.1
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•
•
•
•
•
•
•
•
•
•
Digital Signal Processing Core
Efficient 16-bit 56800E family hybrid controller engine with dual Harvard architecture
As many as 60 Million Instructions Per Second (MIPS) at 60MHz core frequency
Single-cycle 16
×
16-bit parallel Multiplier-Accumulator (MAC)
Four 36-bit accumulators, including extension bits
Arithmetic and logic multi-bit shifter
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Three internal address buses
Four internal data buses
Instruction set supports both DSP and controller functions
Controller style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/EOnCE debug programming interface
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1.1.2
•
•
•
Memory
Harvard architecture permits as many as three simultaneous accesses to program and data memory
Flash security protection feature
On-chip memory, including a low-cost, high-volume Flash solution
— 128KB of Program Flash
— 4KB of Program RAM
— 8KB of Data Flash
— 8KB of Data RAM
— 8KB of Boot Flash
•
EEPROM emulation capability
1.1.3
•
•
•
•
•
•
Peripheral Circuits for 56F8345
Two Pulse Width Modulator modules, each with six PWM outputs, three Current Sense inputs, and
four Fault inputs; fault-tolerant design with dead time insertion; supports both center-aligned and
edge-aligned modes
Four 12-bit, Analog-to-Digital Converters (ADCs), which support four simultaneous conversions
with quad, 4-pin multiplexed inputs; ADC and PWM modules can be synchronized through Timer
C, channels 2 and 3
Two four-input Quadrature Decoders or two additional Quad Timers
Temperature Sensor can be connected, on the board, to any of the ADC inputs to monitor the
on-chip temperature
Four dedicated general-purpose Quad Timers totaling six dedicated pins: Timer C with two pins and
Timer D with four pins
Optional On-Chip Regulator
4
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56F8345 Technical Data
Preliminary
Freescale Semiconductor, Inc.
56F8345 Description
•
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•
•
•
•
•
•
•
•
Freescale Semiconductor, Inc...
•
FlexCAN (CAN Version 2.0 B-compliant) module with 2-pin port for transmit and receive
Two Serial Communication Interfaces (SCIs), each with two pins (or four additional GPIO lines)
Up to two Serial Peripheral Interfaces (SPIs), both with configurable 4-pin port (or eight additional
GPIO lines); SPI 1 can also be used as Quadrature Decoder 1 or Quad Timer B
Computer Operating Properly (COP)/Watchdog timer
Two dedicated external interrupt pins
49 General Purpose I/O (GPIO) pins; 21 pins dedicated to GPIO
External reset input pin for hardware reset
External reset output pin for system reset
Integrated low-voltage interrupt module
JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent,
real-time debugging
Software-programmable, Phase Lock Loop-based frequency synthesizer for the core clock
1.1.4
•
•
•
•
•
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Energy Information
Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
On-board 3.3V down to 2.6V voltage regulator for powering internal logic and memories; can be
disabled
On-chip regulators for digital and analog circuitry to lower cost and reduce noise
Wait and Stop modes available
ADC smart power management
Each peripheral can be individually disabled to save power
1.2 56F8345 Description
The 56F8345 is a member of the 56800E core-based family of hybrid controllers. It combines, on
a single chip, the processing power of a DSP and the functionality of a microcontroller with a
flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost,
configuration flexibility, and compact program code, the 56F8345 is well-suited for many
applications. The 56F8345 includes many peripherals that are especially useful for motion control,
smart appliances, steppers, encoders, tachometers, limit switches, power supply and control,
automotive control, engine management, noise suppression, remote utility metering, industrial
control for power, lighting, and automation applications.
The 56800E core is based on a Harvard-style architecture consisting of three execution units
operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style
programming model and optimized instruction set allow straightforward generation of efficient,
compact DSP and control code. The instruction set is also highly efficient for C/C++ Compilers to
enable rapid development of optimized control applications.
The 56F8345 supports program execution from internal memories. Two data operands can be
accessed from the on-chip data RAM per instruction cycle. The 56F8345 also provides two
external dedicated interrupt lines and up to 49 General Purpose Input/Output (GPIO) lines,
depending on peripheral configuration.
The 56F8345 hybrid controller includes 128KB of Program Flash and 8KB of Data Flash (each
programmable through the JTAG port) with 4KB of Program RAM and 8KB of Data RAM.
A total of 8KB of Boot Flash is incorporated for easy customer-inclusion of field-programmable
56F8345 Technical Data
Preliminary
5
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