512Kx8/256Kx16/128Kx32, 150 - 250ns, PGA
30A169-00
A
4 Megabit 5 Volt CMOS FLASH EEPROM
DPZ128X32XP/XHP
DESCRIPTION:
The DPZ128X32XP/XHP is a 4 megabit 5 Volt only CMOS
Flash EEPROM (Electrically In-System Programmable and
Erasable ROM memory) module. The module is built with
four 128K x 8 FLASH memory devices. The
DPZ128X32XP/XHP can be user configurable as 512K x 8,
256K x 16 or 128K x 32 bits.
The DPZ128X32XP/XHP is ideal for use in systems that
require In-System periodic code updates, or for use as a high
speed nonvolatile storage medium.
FEATURES:
•
User Definable Configuration:
512K x 8, 256K x 16 or 128K x 32
•
Fast Read Access Times: 70, 90, 120, 150ns
•
Low Power:
120mA Maximum Active (32 bit Mode)
400µA Maximum Standby (CMOS)
•
10,000 Erase/Program Cycles Minimum
•
5 Volt Only In-System Programming
•
TTL-Compatible Inputs and Outputs
•
Packages Available:
68- “J” Leaded Plastic Surface Mount Module
68- Gull - Leaded Plastic Surface Mount Module
PIN NAMES
A0 - A16
Address Inputs
I/O0 - I/O31
Data Input/Output
CE0 - CE3
Low Chip Enables
WE
Write Enable
OE
Output Enable
V
DD
Power (+5V)
V
SS
Ground
N.C.
No Connect
PIN-OUT DIAGRAM
FUNCTIONAL BLOCK DIAGRAM
30A169-00
REV. A
This document contains information on a product that is currently released
to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the
right to change products or specifications herein without prior notice.
1
DPZ128X32XP/XHP
DEVICE OPERATION
DATA BUS WIDTH:
The DPZ128X32XP/XHP is configured with separate CE‘s and
data I/O’s to allow the module to be used in an 8 bit, 16 bit or
32 bit environment. When either the software data protect or
the chip erase feature is used, the specific data shown in the
algorithms must be written to each device that the operation is
being perfomed on. An example would be if the module is used
in a 32 bit system, the data called out in the third data load for
the software data protect alogrithm is A0H. The data of
A0A0A0A0H should be written to the DPZ128X32XP/XHP.
READ:
The DPZ128X32XP/XHP is accessed like a Static Ram. When
CE and OE are low and WE is high, the data stored at the
memory location determined by address pins is asserted on the
outputs. The outputs are put in the high impedance state
whenever CE or OE is high. This dual line control gives
designers flexibility in preventing bus contention.
BYTE LOAD:
A byte is loaded into the device by applying a low pulse to WE
or CE with CE or WE low (respectively) and OE high. On the
falling edge of CE or WE, whichever occurs last, the address is
latched. On the rising edge of CE or WE, whichever occurs first,
the data is latched. This operation is used to load data into the
128 byte page for programming or to load software codes for
data protection or 5 volt chip erase.
PROGRAM:
This DPZ128X32XP/XHP is programmed in a page mode only.
A7 to A16 are used to specify the page address and they must
be valid during each high to low transition of WE or CE. A0 to
A6 are used to specify the address of the byte within the 128
byte page. The data can be loaded into the page in any order.
All of the bytes within the page must be written, otherwise any
unwritten bytes will be erased to read FFH. The locations to be
reprogrammed need not be erased prior to programming as
with other FLASH technologies. Each new byte to be loaded
must have its high to low transition of WE or CE within 150µs
of the preceding bytes high to low transition. If a high to low
transition is not detected within 150µs of the last high to low
transition, the internal programming period will begin.
DATA POLLING:
The DPZ128X32XP/XHP features DATA Polling to indicate the
end of a program cycle. During a program cycle an attempted
read of the last byte loaded will result in the complement of the
loaded data on the MSB (most significant bit, I/O7,I/O15,I/O23
and I/O31) of the device or devices being programmed at that
time. When the programming cycle is complete, the data will
be true on all outputs and the next programming cycle can
begin. Data Polling can begin at any time during the
programming period.
Dense-Pac Microsystems, Inc.
TOGGLE BIT:
The DPZ128X32XP/XHP has an additional method for
determining if the program period or erase cycle is completed.
During a program or erase operation, successive attempts to
read data from the device will result in I/O6, I/O14, I/O22 or
I/O30 (depending on the device or devices the operation is
being performed on) toggling between one and zero. Once the
program or erase period has completed, the I/O pin will stop
toggling and valid data can be read. Examining the toggle bit
can begin at any time during the program or erase period.
HARDWARE DATA PROTECTION:
The devices used on the DPZ128X32XP/XHP incorporate
several hardware features for data protection. If V
DD
falls below
3.8V (typ.), the program function is inhibited. During power up,
programming will be inhibited 5ms (typ.) after V
DD
has reached
the V
DD
sense level. Another hardware feature is a noise filter
on CE or WE. Any pulse less than 15ns (typ.) will not initiate a
program cycle. Finally, programming is inhibited by holding
any one of: OE low, CE high or WE high.
SOFTWARE DATA PROTECTION:
The DPZ128X32XP/XHP features software data protection that
can be enabled and disabled by the end user. The software
protection is enabled by writing a series of three commands to
specific addresses with specific data using the page program
timing specifications. Once the software protection is enabled,
the same three commands must precede a program cycle. The
software protection will remain active until the disable
command algorithm is issued. Power transitions will not reset
the software protection. The data will be protected against
inadvertent programming during power transitions. The
DPZ128X23VT/VTP is shipped with the software data
protection disabled.
5 VOLT CHIP ERASE:
Each device on the DPZ128X32XP/XHP can be erased at one
time by using a six byte software code. The erase code consists
of six byte load commands to specific address locations with
specific data patterns. After the command is entered, every
location in the device being erased will be set to a high state
(FFH).
2
30A169-00
REV. A
DPZ128X32XP/XHP
Dense-Pac Microsystems, Inc.
A.C. OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE:
No. Symbol
1
2
3
4
5
t
ACC
t
CE
t
OE
t
DF
t
OH
Parameter
Address to Output Valid
Chip Enable to Output Valid
Output Enable to Output Valid
Chip Enable or Output Enable to Float
4
Output Hold from Chip Enable, Output Enable,
or Address, Whichever Occurs First
70ns
90ns
Min. Max. Min. Max.
70
90
70
90
0
35
0
40
0
25
0
25
0
0
120ns
150ns
Unit
Mn. Max. Min. Max.
120
150
ns
120
150
ns
0
50
0
70
ns
0
30
0
40
ns
0
0
ns
Over operating ranges
READ CYCLE
ADDRESS
CE
OE
DATA I/O
No. Symbol
6
t
AS
7
t
OES
8
t
AH
9
t
CS
10
t
CH
11
t
WP
12
t
DS
13
t
DH
14
t
OEH
15
t
WPH
Address Setup Time
Output Enable Setup Time
Address Hold Time
Chip Select Setup Time
Chip Select Hold Time
Write Pulse Width (Write Enable or Chip Enable)
Data Setup Time
Data Hold Time
Output Enable Hold Time
Write Page Width High
Parameter
A.C. BYTE LOAD CHARACTERISTICS
Min.
0
0
50
0
0
90
35
0
0
100
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1.
2.
3.
4.
All voltages are with respect to V
SS
.
-1.0V min. for pulse width less than 20ns (V
IL
min. = -0.3V
at DC level).
Stresses greater than those under
ABSOLUTE MAXIMUM
RATINGS
may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
This parameter is guaranteed and not 100% tested.
A7 through A16 specify the page address during each high
to low transition of WE (or CE) after the software code has
been entered.
6. OE must be high when WE and CE are both low.
7. All bytes that are not loaded within the page being
programmed will be erased to FF.
8. Toggling either OE or CE or both OE and CE will operate
toggle bit.
9. Beginning and ending state of I/O6 will vary.
10. Any address location may be used but the address should
not vary.
30A169-00
REV. A
5.
4
Analogue and Mixed Signal
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