4 Megabit CMOS SRAM
DPS512S8P/DPS512S8PL/DPS512S8PLL
DESCRIPTION:
The DPS512S8P/PL/PLL is a 512K X 8 high-density,
low-power static RAM module comprised of four
128K X 8 monolithic SRAM’s, an advanced
high-speed CMOS decoder and decoupling capacitors
surface mounted on a co-fired ceramic substrate
having side-brazed leads.
The DPS512S8P/PL/PLL is available in a 600-mil-wide,
32-pin dual-in-line package that conforms to the same
JEDEC standard pin configuration as the future four
megabit monolithics.
The DPS512S8P/PL/PLL operates from a single +5V
supply and all input and output pins are completely
TTL-compatible. The low standby power of the
DPS512S8P/PL/PLL makes it ideal for battery-backed
applications.
FEATURES:
•
524, 288 by 8 Bit Configuration
•
Access Times: 70*, 85, 100, 120, 150ns
•
Low Power Dissipation:
25
µ
W (typ.) Standby (DPS512S8PL/DPS512S8PLL)
40
µ
W (typ.) Standby (DPS512S8P)
375 mW (typ.) Operating
•
2-Volt Data Retention
•
Fully Static Operation - No Clock or Refresh
Required
•
All inputs and Outputs are TTL-Compatible
•
600 mil, 32-pin JEDEC Standard DIP Pinout
*
Available in Commercial only.
PIN NAMES
A0 - A18
Address Inputs
I/O0 - I/O7
Data In/Out
CE
Chip Enable
WE
Write Enable
OE
Output Enable
V
DD
Power (+5V)
V
SS
Ground
PIN-OUT DIAGRAM
FUNCTIONAL BLOCK DIAGRAM
30A034-00
REV. E
This document contains information on a product that is currently released
to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the
right to change products or specifications herein without prior notice.
1
DPS512S8P/PL/PLL
Dense-Pac Microsystems, Inc.
RECOMMENDED OPERATING RANGE
1
Symbol
Characteristic
V
DD
Supply Voltage
V
IH
Input HIGH Voltage
V
IL
Input LOW Voltage
C
Operating
T
A
Temperature
I
Min.
4.5
2.2
-0.5
2
0
-40
Max. Unit
5.5
V
V
DD
+0.3 V
0.8
V
+25
+70
°C
+25
+85
Typ.
5.0
Mode
Not Selected
D
OUT
Disable
Read
Write
H = HIGH
TRUTH TABLE
CE
H
L
L
L
WE
X
H
H
L
L = LOW
OE
X
H
L
X
I/O Pin
HIGH-Z
HIGH-Z
D
OUT
D
IN
Supply
Current
Standby
Active
Active
Active
X = Don’t Care
DC OUTPUT CHARACTERISTICS
Symbol
Parameter
V
OH
HIGH Voltage
V
OL
LOW Voltage
Conditions Min. Max. Unit
I
OH
= -1.0mA 2.4
-
V
I
OL
= 2.1mA
0.4 V
CAPACITANCE
4
: T
A
= 25°C, F = 1.0MHz
ABSOLUTE MAXIMUM RATINGS
3
Symbol
T
STC
T
BIAS
V
DD
V
I/O
Parameter
Max.
Unit
Storage Temperature
-55 to +125
°C
Temperature Under Bias
-10 to + 85
°C
Supply Voltage
1
-0.5 to + 7.0
V
1
Input/Output Voltage
-0.5 to V
DD
+0.5 V
Symbol
C
ADR
C
CE
C
WE
C
OE
C
I/O
Parameter
Address Input
Chip Enable
Write Enable
Output Enable
Data Input/Output
Max.
45
20
45
45
50
Unit
Condition
pF
V
IN
= 0V
DC OPERATING CHARACTERISTICS: Over operating ranges
Symbol
I
IN
I
OUT
I
CC1
Characteristics
Input
Leakage Current
Output
Leakage Current
Active
Supply Current
Operating
Supply Current
Full Standby
Supply Current
Standby Current
Output Low Voltage
Output High Voltage
Test Conditions
V
IN
= 0V to V
DD
V
I/O
= 0V to V
DD
,
CE or OE = V
IH
, or WE = V
IL
P
CE = V
IL
,
V
IN
= V
IH
or V
IL
,
PL
I
OUT
= 0mA
PLL
P
Cycle = min.,
Duty = 100%,
PL
I
OUT
= 0mA
PLL
P
V
IN
≥
V
DD
-0.2V or
PL
V
IN
≤
V
SS
+0.2V,
CE
≥
V
DD
-0.2V
PLL
P
CE = V
IH
,
PL
V
IN
= V
IH
or V
IN
PLL
I
OUT
= 2.1mA
I
OUT
= -1.0mA
TYP.
-
-
30
30
30
75
60
40
8
5
5
4
4
4
-
-
COMMERCIAL
Min.
Max.
INDUSTRIAL
Min.
†
Max.
Unit
µA
µA
mA
-10
-10
+10
+10
50
50
40
110
100
80
400
200
100
12
8
6
0.4
-10
-10
+10
+10
55
55
45
110
100
80
600
300
200
12
10
8
0.4
I
CC2
mA
I
SB1
µA
I
SB2
V
OL
V
OH
mA
V
V
2.4
2.4
† Not available in 70ns.
2
30A034-00
REV. E
Dense-Pac Microsystems, Inc.
DATA RETENTION CHARACTERISTICS
Symbol
V
DR
I
CCDR2
Parameter
Data Retention
Voltage
Data Retention
Supply Current
Data Retention
Supply Current
Test Conditions
CE
≥
V
DR
-0.2V
V
DR
= 2.0V
P
PL
PLL
P
PL
PLL
Typ.
-
4
4
1
4
4
1
-
COMMERCIAL
Min.
Max.
DPS512S8P/PL/PLL
INDUSTRIAL †
Min.
Max.
Unit
V
µA
2.0
5.5
180
80
40
200
100
50
2.0
5.5
270
120
60
300
150
75
I
CCDR3
t
CDR
t
R
V
DR
= 3.0V
µA
ns
ms
Chip Disable to Data Retention Time
Recovery Time
t
RC
= Read Cycle Timing
0
5
0
5
† Not Available in 70ns.
AC TEST CONDITIONS
Input Pulse Levels
Input Pulse Rise and Fall Times
Input and Output
Timing Reference Levels
* Transition measured between 0.8V and 2.2V.
0V to 3.0V
5ns *
1.5V
Figure 1. Output Load
** Including Probe and Jig Capacitance.
+5V
1.8KΩ
Output Load
Load
1
2
C
L
100pF
5pF
Parameters Measured
except t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
WHZ
,
and t
WLZ
t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
WHZ
, and t
WLZ
D
OUT
C
L
**
990Ω
AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE: Over operating ranges
No. Symbol
1
2
3
4
5
6
7
8
9
t
RC
t
AA
t
CO
t
OV
t
OH
t
CLZ
t
OLZ
t
CHZ
t
OHZ
Parameter
Read Cycle Time
Address Access Time
Chip Enable to Output Valid
Output Enable to Output Valid
Output Hold from Address Change
Chip Enable to Output in LOW-Z
4, 6
Output Enable to Output in LOW-Z
4, 6
Chip Enable to Output in HIGH-Z
4, 6
Output Enable to Output in HIGH-Z
4, 6
70ns
††
Min.
85ns
85
100ns
100
120ns
120
150ns
Max.
Max. Min.
Max. Min.
Max. Min.
Max. Min.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
70
70
70
45
10
5
0
35
30
150
120
120
50
150
150
60
10
5
0
50
35
60
45
85
85
45
10
5
0
45
30
10
5
0
100
100
45
10
5
0
45
30
AC OPERATING CONDITIONS AND CHARACTERISTICS - WRITE CYCLE: Over operating ranges
7
No. Symbol
10
11
12
13
14
15
16
17
18
19
t
WC
t
AW
t
CW
t
DW
t
DH
t
WP
t
AS
t
AH
t
WHZ
t
WLZ
Parameter
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Data to Write Time Overlap
Data Hold Time from Write Time
Write Pulse Width
Address Set-up Time ***
Address Hold Time
Write Enable to Output in HIGH-Z
4, 6
Write Enable to Output in LOW-Z
4, 6
70ns
††
Min.
85ns
85
80
80
35
0
55
0
5
100ns
100
90
90
35
0
65
0
5
120ns
120
105
105
40
0
75
0
5
150ns
Max.
Max. Min.
Max. Min.
Max. Min.
Max. Min.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
70
65
65
35
0
55
0
5
30
5
150
115
115
50
0
85
0
5
35
40
5
30
5
5
30
5
*** Valid for both Read and Write Cycles.
†† Available in commercial only.
30A034-00
REV. E
3
DPS512S8P/PL/PLL
DATA RETENTION WAVEFORM
Dense-Pac Microsystems, Inc.
V
DD
4.5V
2.2V
V
DR
CE
V
SS
READ CYCLE 1:
Address Controlled. WE is HIGH. CE and OE are LOW.
ADDRESS
DATA I/O
READ CYCLE 2:
CE Controlled. WE is HIGH.
ADDRESS
CE
OE
DATA I/O
4
30A034-00
REV. E
Dense-Pac Microsystems, Inc.
DPS512S8P/PL/PLL
WRITE CYCLE 1
:
WE Controlled. OE is LOW.
ADDRESS
CE
WE
DATA I/O
WRITE CYCLE 2:
CE Controlled. OE is HIGH.
ADDRESS
CE
WE
DATA I/O
WAVEFORM KEY
Data Valid
Transition from
HIGH to LOW
Transition from
LOW to HIGH
Data Undefined
or Don’t Care
30A034-00
REV. E
5
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