DPSD64MX4TY5-DP-XXP12 datasheet, PDF

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DPSD64MX4TY5-DP-XXP12: DescriptionSynchronous DRAM, 64MX4, CMOS, PDSO54, STACKED, TSOP2-54; Categorystorage storage; File Size135KB，2 Pages; ManufacturerB&B Electronics Manufacturing Company

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DPSD64MX4TY5-DP-XXP12 Overview

Synchronous DRAM, 64MX4, CMOS, PDSO54, STACKED, TSOP2-54

DPSD64MX4TY5-DP-XXP12 Parametric

Parameter Name	Attribute value
Maker	B&B Electronics Manufacturing Company
Parts packaging code	TSOP2
package instruction	ATSOP,
Contacts	54
Reach Compliance Code	unknow
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PDSO-G54
length	22.479 mm
memory density	268435456 bi
Memory IC Type	SYNCHRONOUS DRAM
memory width	4
Number of functions	1
Number of ports	1
Number of terminals	54
word count	67108864 words
character code	64000000
Operating mode	SYNCHRONOUS
organize	64MX4
Package body material	PLASTIC/EPOXY
encapsulated code	ATSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, PIGGYBACK, THIN PROFILE
Certification status	Not Qualified
Maximum seat height	2.59 mm
self refresh	YES
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	DUAL

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ADVANCE D COM P ON E NTS PACKAG I NG

256 Megabit Synchronous DRAM

DPSD64MX4TY5

DESCRIPTION:

The Memory Stack™ series is a family of interchangeable memory devices. The 256 Megabit SDRAM assembly utilizes the

space saving LP-Stack™ technology to increase memory density. This stack is constructed with two 128Mb (32M x 4)

SDRAMs.

This 256Mb LP-Stack™ has been designed to fit in the

same footprint as the 128Mb (32M x 4) SDRAM TSOPII

monolithic. This stack allows for system upgrade without

electrical or mechanical redesign, providing an alternative

low cost memory solution.

FEATURES:

•

Electrical characteristics meet semiconductor

manufacturers’ datasheets

Memory organization:

(2) 128Mb memory devices. Each device arranged

as 32M x 4 bits (8M x 4 bits x 4 banks)

Memory stack organization:

64M x 4 bits (16M x 4 bits x 4 banks)

•

JEDEC approved, 2 Rank stack pinout and footprint

(with 2 CS, 1 CKE)

Optimized for RDIMMs

IPC-A-610, class 2, manufacturing standards

Lead free manufacturing process

Package: 54-Pin TSOPII stack

PIN-OUT DIAGRAM

VCC

VCCQ

DQ0

VSSQ

VCCQ

DQ1

VSSQ

VCC

CS1

CAS

RAS

CS0

BA0

BA1

A10

VCC

•

(TOP VIEW)

VSS

VSSQ

DQ3

VCCQ

VSSQ

DQ2

VCCQ

VSS

DQM

CLK

CKE

A11

VSS

A0-A11

BA0, BA1

DQ0-DQ3

CAS

RAS

DQM

CKE

CLK

CS0, CS1

CCQ

SSQ

30A214-00

REV. D 6/03

PIN NAMES

Row Address:

Column Address:

Data In/Data Out

A0-A11

A0-A9, A11

FUNCTIONAL BLOCK DIAGRAM

CS1

CS0

RAS

CAS

CLK

DQM

CKE

A0-A11

BA0,BA1

(8M x 4 bits x 4 banks)

Column Address Strobe

Row Address Strobe

Data Write Enable

Data Input/Output Mask

Clock Enable

System Clock

Chip Selects

Power Supply/Ground

Data Output Power/Ground

No Connect

128Mb SDRAM

(8M x 4 bits x 4 banks)

Bank Select Address

DQ0-DQ3

This document contains information on a product that is currently released to production at DPAC Technologies.

DPAC reserves the right to change products or specifications herein without prior notice.

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