PC109
Host Bridge for PowerPC
Datasheet - Preliminary
Features
•
Processor Interface
– Supports PowerPC Processors
• Freescale MPC74xx
• IBM PPC 750xx
– Operates up to 200 MHz in Single Processor Mode
– Operates up to 167 MHz in Dual Processor Mode
•
PCI/X Interface
– Support PCI 2.3 and PCI-X 1.0 Modes
– Operates up to 133 MHz
– Supports PCI/X Host or Agent Operation
– Supports Compact PCI Hot Swap
•
Memory Controller
– Supports DDR2-400 Devices
– Operates up to 200 MHz
– Enhanced Memory Pipeline
•
Other Features
– Integrated Bus Arbiters for Processors and PCI/X Devices
– Integrated Power Management of Processors and Memory Devices
– Four Independent DMA/XOR Channels
– Clock Generator with Spread-spectrum Capability
– Two Independent Gigabit Ethernet Ports
– HLP Interface for Flash and Other Simple I/O Devices
– Two UARTs
– 16-bit Parallel GPIO Port
– I
2
C/EEPROM Interface
– Programmable Interrupt Controller
– JTAG Support (Boundary Scan) with Register Access Capability
– Packaging: 1023-pin, 33x33 mm, FCBGA, RoHS-compliant and HITCE (TBC), Pin Compatible with Tsi108
– Power Consumption: 2.5W Typical, 3.8W Maximum
Description
The PC109 is an advanced host bridge for PowerPC processors that supports PCI-X, DDR2-400 SDRAM, Gigabit Ether-
net, and Flash. The device contains numerous integrated features that enable customers to reduce system design
complexity and system costs.
Visit our website: www.e2v.com
for the latest version of the datasheet
e2v semiconductors SAS 2011
0838C–HIREL–07/11
PC109 [Preliminary]
Scope
The PC109 Hardware Manual discusses electrical, physical, and board layout information for the PC109.
It is intended for hardware engineers who are designing system interconnect applications with these
devices.
Screening
•
Full Military Temperature Range (T
J
= -55°C, +125°C)
•
Industrial Temperature Range (T
J
= -40°C, +110°C)
1. Block Diagram
60x/MPX 200-MHz Bus, 64-bit Data, 32/36-bit Address
Memory Controller
Spread-spectrum
Clock Generator
Clock
Generator
Processor Interface
Arbiter
DDR2-400,
8-bit ECC
Four External
Interrupts
Interrupt
Controller
Four DMA
Channels
DMA
Ethernet Controller
Process and
Memory Power
Management
Power
Mgmt
Switch
Fabric
Two
10/100/1G
Ports
Two UARTs
UART
Connects to
Serial PROMs
I2C
Host Local
Port
32-bit
Flash &
I/O Access
IEEE1149.1
Boundry
Scan
JTAG
80B5020_BK001_04
GPIO
PCI-X Interface
Arbiter
16-bit I/O Port
133-MHz PCI-X Bus
Seven Bus
66-MHz/64-bit PCI Bus, 64-bit Data Masters
2. Features
2.1
Enhancing System Performance
The advanced Switch Fabric architecture of the PC109 allows designers to significantly enhance system
performance. The Eternet Controller and PCI-X Interface offer superior data transfer rates. In addition,
CPU to memory performance is exceptional due to features like configurable port arbitration priority and
queuing reads ahead of writes.
2.2
Minimizing System Cost
The PC109 feature set provides system designers with an array of integrated functionality to assist in
lowering overall system cost, such as an integrated Clock Generator with spread-spectrum capabilities,
a DDR2-400 Memory Controller, and internal processor and PCI/X bus arbiters.
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PC109 [Preliminary]
2.3
Simplifying Design
PC109’s flexible configuration options empower designers to develop their systems quickly and effi-
ciently. Selection of PCI/PCI-X modes, an integrated Clock Generator, DDR2 support, and the ability to
configure it as a PCI Host/Agent, all enable the PC109 to be used in a range of applications. The JTAG
Interface also simplifies the debug process by allowing access to PC109’s registers without impacting
active transactions.
2.4
Effective Power Management
The PC109 is the lowest, power-consuming host bridge on the market. It minimizes active power by dis-
abling unused ports and clocks, while its integrated Clock Generator saves power over discrete devices.
Its support for DDR2 provides memory power savings of up to 50 percent when compared with DDR. It
also supports precharge power-down and quiet stand-by power reduction modes on memory. In addi-
tion, the PC109 conforms to the PCI Bus Power Management Interface Specification.
2.5
Document Conventions
This document uses a variety of conventions to establish consistency and to help you quickly locate
information of interest. These conventions are briefly discussed in the following sections.
Non-differential Signal Notation
Non-differential signals are either active-low or active-high. An active-low signal has an active state of
logic 0 (or the lower voltage level), and is denoted by a lowercase
n.
An active-high signal has an active
state of logic 1 (or the higher voltage level), and is not denoted by a special character. The following
table illustrates the non-differential signal naming convention.
State
Active low
Active high
Single-line Signal
NAMEn
NAME
Multi-line Signal
NAMEn[3]
NAME[3]
Differential Signal Notation
Differential signals consist of pairs of complement positive and negative signals that are measured at the
same time to determine a signal’s active or inactive state (they are denoted by
_P
and
_N,
respectively).
The following table illustrates the differential signal naming convention.
State
Inactive
Active
Single-line Signal
NAME_P = 0
NAME_N = 1
NAME_P = 1
NAME_N = 0
Multi-line Signal
NAME_P[3] = 0
NAME_N[3] = 1
NAME_P[3] is 1
NAME_N[3] is 0
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3. General Parameters
Table 3-1
provides a summary of the general parameters of the PC109
Table 3-1.
Parameter
Technology
Die size
Packages
Core power supply
I/O power supply
Device Parameters
Description
130 nm
8,71 mm x 8,92 mm
1023 PBGA and HITCE
1,2V ± 5%
3,3V ± 0,3V and 1,8 ± 5%
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PC109 [Preliminary]
4. Signal Description
Figure 4-1.
PC109 Microprocessor Signal Groups
PB_A[0:35]
PB_AACKn
SD_SYSCLK
SD_A[15:0]
SD_BA[2:0]
SD_CASn
SD_CLK_P[5:0]/SD_CLK_N[5:0]
SD_CLKEN[1:0]
SD_CLKFBI_PSD_CLKFBI_N
SD_CLKFBO_P/SD_CLKFBO_N
SD_CSn[3:0]
SD_DQ[63:0]
SD_DQS_P[17:0]/SD_DQS_N[17:0]
SD_CB[7:0]
SD_I2C_CLK
SD_I2C_SD
SD_RASn
SD_VREF[1:0]
SD_WEn
SD_ODT[3:0]
SD_DLL_TEST 1:0
E_0_TCG[9:0]
E_0_RCG[9:0]
E_0_ PCRS_SDET
E_0_PCOL_R
E_0_ECMDT
E_0_EWRAP
E_0_PRBSEN
E_0_PRBS_PASS
E_0_RXCLK
E_0_TXCLK
E_1_TCG[9:0]
E_1_RCG[9:0]
PB_AP[0:4]
PB_ARTRYn
PB_BGn[0:1]
PB_BRn[0:1]
PB_D[0:63]
PB_DBGn[0:1]
PB_DP[0:7]
PB_DRDYn[0:1]
PB_DTI[0:2]
PB_GBLn
PB_HITn[0:1]
PB_INTn[0:3]
PB_QREQn[0:1]
PB_QACKn[0:1]
PB_RSTn
PB_RSTOD
PB_SYSCLK
PB_TAn
PB_TEAn
PB_TBSTn
PB_TSn
PB_TSIZ[0:2]
PB_TT[0:4]
PB_SENSE
PCI_ACK64n
PCI_AD[63:0]
PCI_CBEn[7:0]
PCI_CLK
PCI_DEVSELn
PCI_FRAMEn
PCI_GNTn[7:1]
PCI_IDSEL
PCI_INTAn
PCI_INTBn
Memory Controller Signals
Processor Interface
Ethernet Controller
E_1_PCRS_SDET
E_1_PCOL_RBCM
E_1_ECMDT
E_1_EWRAP
E_1_PRBSEN
E_1_PRBS_PASS
E_1_RXCLK
E_1_TXCLK
E_MDC
E_MDIO
E_REF125
E_GTXCLK[1:0]
PC109
PCI_INTCn
PCI_INTDn
PCI_IRDYn
PCI_M66EN
PCI_PAR
PCI_PCIX CAP[1:0]
PCI_PAR64
I_PC
PCI_PERRn
PCI_PMEn
PCI_REQn[7:1]
PCI/X Interface Signals
Interrupt Controller Signals
I2C Interface Signals
INT[3:0]
I2C_SCLK
I2C_SD
HLP_AD[31:0]
HLP_CSn[3:0]
HLP_LE
PCI_REQ64n
PCI_RSTn
PCI_RSTDIR
PCI_SERRn
PCI_STOPn
PCI_TRDYn
PCI_ENUMn
PCI_ES
PCI_HEALTHYn
PCI_HS64ENn
PCI_LEDn
PCI_SENSE
HLP Interface Signals
HLP_RDYn
HLP_OEn
HLP_WEn
GPIO Interface Signals
GPIO[15:0]
U_0_RX
U_0_TX
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRSTn
TEST_ON
TEST_BIDR_CTL
TEST_TM[3:0]
PB_PLL_AVDD
PB_PLL_AVSS
PCI_PLL_AVDD
PCI_PLL_AVSS
SD_PLL_AVDD
SD_PLL_AVSS
CLKGEN_PLL_AVDD
CLKGEN_PLL_AVDD
CLKGEN_PLL_AVSS
CLKGEN_PLL_AVSS
UART Interface Signals
U_1_RX
U_1_TX
CG_REF
CG_PB_CLKO[2:0]
CG_PCI_CLKO[3:0]
JTAG Interface signals
Clock Generator Signals
CG_PB_SELECT[2:0]
CG_SD_SELECT[2:0]
VDD (50)
VDD_PC (49)
VDD_PB (45)
Power Supply Signals
VDD_SD (39)
VSS (50)
VSS_IO (160)
PLL Power Signals
Switch Fabric Signals
OCN_RSTn
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