PC8548EVGHYUAUGA datasheet, PDF

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PC8548EVGHYUAUGA: DescriptionMicroprocessor, 32-Bit, 133MHz, CMOS, PBGA783, 29 X 29 MM, 2.86 MM HEIGHT, 1 MM PITCH, FLIP CHIP, BGA-783; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，102 Pages; Manufacturere2v technologies

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PC8548EVGHYUAUGA Overview

Microprocessor, 32-Bit, 133MHz, CMOS, PBGA783, 29 X 29 MM, 2.86 MM HEIGHT, 1 MM PITCH, FLIP CHIP, BGA-783

PC8548EVGHYUAUGA Parametric

Parameter Name	Attribute value
Maker	e2v technologies
Parts packaging code	BGA
package instruction	BGA,
Contacts	783
Reach Compliance Code	compli
ECCN code	3A001.A.2.C
Other features	ALSO REQUIRES 2.5V OR 3.3V SUPPLY
Address bus width	64
bit size	32
boundary scan	YES
maximum clock frequency	166 MHz
External data bus width	64
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-PBGA-B783
length	29 mm
low power mode	YES
Number of terminals	783
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Certification status	Not Qualified
Maximum seat height	2.86 mm
speed	133 MHz
Maximum supply voltage	1.26 V
Minimum supply voltage	1.14 V
Nominal supply voltage	1.2 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	29 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR

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PC8548E

PowerQUICC III Integrated Processor

Datasheet -

Preliminary Specification

Features

•

Embedded e500 Core, Initial Offerings up to 1.2 GHz

– Dual Dispatch Superscalar, 7-stage Pipeline Design with out-of-order Issue and

Execution

– 3065 MIPS at 1333 MHz (Estimated Dhrystone 2.1)

36-bit Physical Addressing

Enhanced Hardware and Software Debug Support

Double-precision Embedded Scalar and Vector Floating-point APUs

Memory Management Unit (MMU)

Integrated L1/L2 Cache

– L1 Cache-32 KB Data and 32 KB Instruction Cache with Line-locking Support

– L2 Cache-512 KB (8-Way Set Associative); 512 KB/256 KB/128 KB/64 KB Can Be Used As SRAM

– L1 and L2 Hardware Coherency

– L2 Configurable As SRAM, Cache and I/O Transactions Can Be Stashed Into L2 Cache Regions

Integrated DDR Memory Controller With Full ECC Support, Supporting:

– 200 MHz Clock Rate (400 MHz Data Rate), 64-bit, 2.5V/2.6V I/O, DDR SDRAM

Integrated Security Engine Supporting DES, 3DES, MD-5, SHA-1/2, AES, RSA, RNG, Kasumi F8/F9 and ARC-4 Encryption

Algorithms

Four On-chip Triple-speed Ethernet Controllers (GMACs) Supporting 10- and 100-Mbps, and 1-Gbps Ethernet/IEEE*802.3

Networks with MII, RMII, GMII, RGMII, RTBI and TBI Physical Interfaces

– TCP/IP Checksum Acceleration

– Advanced QoS Features

General-purpose I/O (GPIO)

Serial RapidIO and PCI Express High-speed Interconnect Interfaces, Supporting

– Single x8 PCI Express, or Single x4 PCI Express and Single 4x Serial RapidIO

On-chip Network (OCeaN) Switch Fabric

Multiple PCI Interface Support

– 64-bit PCI 2.2 Bus Controller (Up to 66 MHz, 3.3V I/O)

– 64-bit PCI-X Bus Controller (Up to 133 MHz, 3.3V I/O), or Flexibility to Configure Two 32-bit PCI Controllers

166 MHz, 32-bit, 3.3V I/O, Local Bus with Memory Controller

Integrated Four-channel DMA Controller

Dual I2C and Dual Universal Asynchronous Receiver/Transmitter (DUAR) Support

Programmable Interrupt Controller (PIC), IEEE 1149.1 JTAG Test Access Port

1.1V Core Voltage with 3.3V and 2.5V I/O, 783-pin HITCE Package

•

Visit our website: www.e2v.com

for the latest version of the datasheet

e2v semiconductors SAS 2007

0831B–HIREL–12/07

PC8548E [Preliminary]

2. Features Overview

The following list provides an overview of the PC8548E feature set:

• High-performance 32-bit Book E–enhanced core that implements the PowerPC

architecture

– 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches

can be locked entirely or on a per-line basis, with separate locking for instructions and data.

– Signal-processing engine (SPE) APU (auxiliary processing unit). Provides an extensive

instruction set for vector (64-bit) integer and fractional operations. These instructions use

both the upper and lower words of the 64-bit GPRs as they are defined by the SPE APU.

– Double-precision floating-point APU. Provides an instruction set for double-precision (64-bit)

floating-point instructions that use the 64-bit GPRs.

– 36-bit real addressing

– Embedded vector and scalar single-precision floating-point APUs. Provide an instruction set

for single-precision (32-bit) floating-point instructions.

– Memory management unit (MMU). Especially designed for embedded applications. Supports

4-Kbyte–4-Gbyte page sizes.

– Enhanced hardware and software debug support

– Performance monitor facility that is similar to, but separate from, the PC8548E performance

monitor

The e500 defines features that are not implemented on this device. It also generally defines some

features that this device implements more specifically. An understanding of these differences can be

critical to ensure proper operations.

• 512-Kbyte L2 cache/SRAM

– Flexible configuration.

– Full ECC support on 64-bit boundary in both cache and SRAM modes

– Cache mode supports instruction caching, data caching, or both.

– External masters can force data to be allocated into the cache through programmed memory

ranges or special transaction types (stashing).

– 1, 2, or 4 ways can be configured for stashing only.

– Eight-way set-associative cache organization (32-byte cache lines)

– Supports locking entire cache or selected lines. Individual line locks are set and cleared

through Book E instructions or by externally mastered transactions.

– Global locking and flash clearing done through writes to L2 configuration registers

– Instruction and data locks can be flash cleared separately.

– SRAM features include the following:

– I/O devices access SRAM regions by marking transactions as snoopable (global).

– Regions can reside at any aligned location in the memory map.

– Byte-accessible ECC is protected using read-modify-write transaction accesses for smaller-

than-cache-line accesses.

• Address translation and mapping unit (ATMU)

– Eight local access windows define mapping within local 36-bit address space.

– Inbound and outbound ATMUs map to larger external address spaces.

– Three inbound windows plus a configuration window on PCI/PCI-X and PCI Express

0831B–HIREL–12/07

e2v semiconductors SAS 2007

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