– Four PCI Express controllers (two support PCIe 2.0
and two support PCIe 3.0)
– Two Serial RapidIO 2.0 controllers running at up to 5
GBaud with Type 11 messaging and Type 9 data
streaming support
•
Additional peripheral interfaces
– Two Serial ATA (SATA 2.0) controllers
– Two high‐speed USB 2.0 controllers with integrated
PHY
– Enhanced secure digital host controller
(SD/MMC/eMMC)
– Enhanced Serial peripheral interface (eSPI)
– Four I2C controllers
– Four 2‐pin UARTs or two 4‐pin UARTs
– Integrated flash controller supporting NAND and NOR
flash
•
Three 8‐channel DMA engines
•
896 FC‐PBGA package, 25 mm × 25 mm, 0.8mm pitch
Whilst Teledyne e2v Semiconductors SAS has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the
consequences of any use thereof and also reserves the right to change the specification of goods without notice. Teledyne e2v Semiconductors SAS accepts no
liability beyond the set out in its standard conditions of sale in respect of infringement of third party patents arising from the use of the devices in accordance with
information contained herein.
Teledyne e2v Semiconductors SAS, avenue de Rochepleine 38120 Saint-Egrève, France
Telephone: +33 (0)4 76 58 30 00
Contact Teledyne e2v by e-mail: hotline-std@teledyne-e2v.com or visit www.teledyne-e2v.com for global sales and operations centres
1170D–HIREL–10/18
Teledyne e2v Semiconductors SAS 2018
Holding Company: Teledyne e2v Semiconductors SAS
T2080 [Preliminary]
1.
OVERVIEW
The T2080 QorIQ integrated multicore communications processor combines 4 dualthreaded cores built on Power
Architecture
®
technology with high‐performance data path acceleration and network and peripheral bus inter‐
faces required for networking, telecom/datacom, wireless infrastructure, and military/aerospace applications.
This chip can be used for combined control, data path, and application layer processing in routers, switches, gate‐
ways, and general‐purpose embedded computing systems. Its high level of integration offers significant
performance benefits compared to multiple discrete devices, while also simplifying board design.
This figure shows the block diagram of the chip.
Figure 1‐1.
Block diagram
Power Architecture
e6500
Power Architecture
e6500
Power Architecture
e6500
Power Architecture
e6500
32 KB
D-Cache
32 KB
I-Cache
32 KB
D-Cache
32 KB
I-Cache
32 KB
D-Cache
32 KB
I-Cache
32 KB
D-Cache
32 KB
I-Cache
P
re-Fetch
2 MB Banked L2
512 KB
Plat Cache
64-bit DDR3/3L
with ECC
MPIC
PreBoot Loader
Security Monitor
Internal BootROM
Power mgmt
SDXC/eMMC
eSPI
2x DUART
CoreNet
TM
Coherency Fabric
PAMU
PAMU
PAMU (peripheral access management unit)
FM an
SEC
PME
DCE
QMan
BMan
H iG ig
Pars e, clas sify,
dis tribute
B u ffer
DCB
Real-time
debug
3x DMA
SATA 2.0
SATA 2.0
Watch point
cross-
trigger
Perf
Trace
Monitor
RMan
4 x 1 /2 .5 /10 G
1GE
1GE
1GE
SRIO
SRIO
PCIe
PCle
PCle
PCle
4x I
2
C
IFC
2x USB2.0 w/PHY
Clocks/Reset
GPIO
CCSR
1GE
Aurora
8 lanes up to 10 GHz SerDes
8 lanes up to 8 GHz SerDes
2.
2.1
PIN ASSIGNMENTS
896 ball layout diagrams
This figure shows the complete view of the T2080 ball map diagram. Figure 2‐2, Figure 2‐3, Figure 2‐4, and Figure
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