Philips Semiconductors
Product specification
Quad 2-input NAND gate
FEATURES
•
Complies with JEDEC standard no. 8-1A
•
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
•
Specified from
−40
to +85
°C
and
−40
to +125
°C.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns.
DESCRIPTION
74HC00; 74HCT00
The 74HC00/74HCT00 are high-speed Si-gate CMOS
devices and are pin compatible with low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard no. 7A.
The 74HC00/74HCT00 provide the 2-input NAND
function.
TYPICAL
SYMBOL
t
PHL
/t
PLH
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. For 74HC00 the condition is V
I
= GND to V
CC
.
For 74HCT00 the condition is V
I
= GND to V
CC
−
1.5 V.
FUNCTION TABLE
See note 1.
INPUT
nA
L
L
H
H
Note
1. H = HIGH voltage level;
L = LOW voltage level.
nB
L
H
L
H
OUTPUT
nY
H
H
H
L
PARAMETER
propagation delay nA, nB to nY
input capacitance
power dissipation capacitance per gate notes 1 and 2
CONDITIONS
74HC00
C
L
= 15 pF; V
CC
= 5 V
7
3.5
22
74HCT00
10
3.5
22
ns
pF
pF
UNIT
2003 Jun 30
2
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74HC00; 74HCT00
handbook, halfpage
1A
1
VCC
14
13
12
4B
4A
4Y
B
3B
3A
handbook, halfpage
1B
1Y
2A
2B
2Y
2
3
4
5
6
7
Top view
GND
8
3Y
A
Y
MNA211
GND
(1)
11
10
9
MNA950
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
Fig.2 Pin configuration DHVQFN14.
Fig.3 Logic diagram (one gate).
handbook, halfpage
handbook, halfpage
1
2
&
3
1
2
4
5
9
10
12
13
1A
1B
2A
2B
3A
3B
4A
4B
1Y
3
4
&
6
2Y
6
5
3Y
8
9
10
&
8
4Y
11
12
&
11
MNA212
13
MNA246
Fig.4 Function diagram.
Fig.5 IEC logic symbol.
2003 Jun 30
4
Philips Semiconductors
Product specification
Quad 2-input NAND gate
RECOMMENDED OPERATING CONDITIONS
74HC00
SYMBOL
V
CC
V
I
V
O
T
amb
PARAMETER
supply voltage
input voltage
output voltage
operating ambient
temperature
input rise and fall times
CONDITIONS
MIN.
2.0
0
0
see DC and AC
−40
characteristics per
device
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
−
−
−
TYP.
5.0
−
−
+25
MAX.
6.0
V
CC
V
CC
+125
74HC00; 74HCT00
74HCT00
UNIT
MIN.
4.5
0
0
−40
TYP.
5.0
−
−
+25
MAX.
5.5
V
CC
V
CC
+125
V
V
V
°C
t
r
, t
f
−
6.0
−
1000
500
400
−
−
−
−
6.0
−
−
500
−
ns
ns
ns
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
V
CC
I
IK
I
OK
I
O
I
CC
, I
GND
T
stg
P
tot
Note
1. For DIP14 packages: above 70
°C
derate linearly with 12 mW/K.
For SO14 packages: above 70
°C
derate linearly with 8 mW/K.
For SSOP14 and TSSOP14 packages: above 60
°C
derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60
°C
derate linearly with 4.5 mW/K.
PARAMETER
supply voltage
input diode current
output diode current
output source or sink
current
V
CC
or GND current
storage temperature
power dissipation
T
amb
=
−40
to +125
°C;
note 1
V
I
<
−0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V
−0.5
V < V
O
< V
CC
+ 0.5 V
CONDITIONS
−
−
−
−
−65
−
MIN.
−0.5
MAX.
+7.0
±20
±20
±25
±50
+150
500
V
mA
mA
mA
mA
°C
mW
UNIT
2003 Jun 30
5
京公网安备 11010802033920号
EEWORLD
