Using High-Speed CMOS
and Advanced CMOS Logic
in Systems With Multiple V
CC
Supplies
or Partial Power Down
Rick Curtis
Texas Instruments Incorporated
SCLA008
April 1996
1
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2
Using High-Speed CMOS and Advanced CMOS Logic
in Systems With Multiple V
CC
Supplies or Partial Power Down
CMOS devices offer a designer many desirable features, the most important one being low-power consumption. However, in
some systems a designer finds that even the low-power consumption of CMOS is insufficient to meet power supply constraints.
Therefore, some designers use partial system power-down or multiple V
CC
supplies to meet their system power requirements.
When a system uses multiple V
CC
supplies or partial power down, designers must take into account several important device
parameters when high-speed CMOS (HC) or advanced CMOS (ACL) devices are used. This is necessary to avoid excessive
power dissipation and prevent damage that could lead to a degradation in the reliability of the device. These parameters are
the continuous input and output diode currents (I
IK
and I
OK
) and the continuous output current (I
O
). I
IK
and I
OK
refer to the
continuous current flowing through the input and output electrostatic discharge (ESD) protection circuits. Figure 1 shows
functionally equivalent schematics of the ESD structures for HC and ACL devices.
VCC
VCC
Input
Output
HC-Equivalent ESD Structure
VCC
VCC
Input
Output
ACL-Equivalent ESD Structure
Figure 1. Simplified ESD Structures for HC and ACL Devices
I
O
is the continuous current flowing through one of the two output transistors. Table 1 shows the absolute maximum rating
for I
IK
, I
OK
, and I
O
for both HC and ACL devices, as listed on device data sheets.
3
Table 1. Absolute Maximum Values for I
IK
, I
OK
, and I
O
ABSOLUTE MAXIMUM
PARAMETER
HIGH-SPEED CMOS
(HC)
±25
mA (standard)
±35
mA (high-current)
±20
mA
±20
mA
ADVANCED CMOS
(ACL)
±50
mA
±20
mA
±20
mA
IO
IIK
IOK
To understand how I
IK
, I
OK
, and I
O
can affect a system design, consider an example of a partial system power down. Figure 2
shows a partial power-down situation where a device powered with V
CC
= 5 V is driving a device without power applied. The
input voltage to the nonpowered device exceeds V
CC
by more than the threshold voltage (0.6 V to 0.8 V), causing the ESD
protection structure to conduct whenever the output of the driver is in a high state. Therefore, the driving device powers up
the receiving device and any other device sharing the same V
CC
line. If no current limiting is provided, the maximum I
O
of
the driving device and the maximum I
IK
of the receiving device could be exceeded.
VCC = 5 V
VCC = 0 V
Figure 2. Example of Partial System Power Down
Several methods are available to protect the driving and receiving devices during partial system power down. If the driving
device has 3-state outputs, placing the outputs in the high-impedance state provides the best solution. However, if this is not
a viable option, some method of current limiting must be provided. Figure 3 shows several methods that can be used, with
current-limiting series resistors being the simplest. The value of the resistor is chosen to limit the current into the receiving
device to less than 20 mA. The major drawback to using a current-limiting resistor is power dissipation. Another drawback
is the effect that the resistor has on the input transition time at the receiving device during normal system operation. If the total
capacitance of the interconnects and receiving devices is high (i.e., a high-capacitance bus), a current-limiting resistor increases
the input transition time. A system designer must ensure that the addition of the resistor does not increase the input transition
time above the maximum input transition time of the receiving device.
A second method of current limiting involves the use of a pullup resistor and a diode (see Figure 3). The advantage of this
method is that it allows the use of a large resistance, thereby holding power dissipation to a minimum. The disadvantage of
this method is that it requires the use of additional components and results in a higher value of V
IL
at the receiving device.
VCC = 5 V
R
VCC = 0 V
Resistor Current Limiting
VCC = 5 V
R
VCC = 0 V
Resistor-Diode Current Limiting
Figure 3. Current Limiting for a Partial System Power Down
4
A second example of how a partial power down can cause unwanted operation is the case of two drivers connected to the same
bus with one device powered down, as shown in Figure 4. In this case, the first bus driver attempts to power up the second bus
driver and any other devices sharing the same V
CC
line through the output ESD structure of the unpowered device.
VCC = 5 V
VCC = 5 V
VCC = 0 V
Figure 4. Partial Power Down With Bus Drivers
Several methods are available to solve this type of problem. One method is simply to use a current-limiting resistor as outlined
above. Another solution is to isolate the unpowered driver from the V
CC
line by putting a diode between the power pin and
the V
CC
supply. If the unpowered device is a transceiver, pullup or pulldown resistors are required on the output control inputs
to disable the outputs. Not disabling the transceiver outputs allows the transceiver to power up the unpowered devices that are
driven by its outputs. When an isolating diode is used, the V
CC
at the driver is always a diode forward drop below the voltage
of the supply, resulting in a degradation of V
OH
. Figure 5 illustrates these circuit solutions.
VCC = 5 V
VCC = 5 V
VCC = 0 V
R
Current-Limiting Resistor
VCC = 5 V
VCC = 5 V
VCC = 0 V
Diode Isolation (for a Transceiver, Disable Outputs)
Figure 5. Current Limiting for Bus Drivers During Partial Power Down
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