UM10398
LPC111x/LPC11Cxx User manual
Rev. 12.1 — 7 August 2013
User manual
Document information
Info
Keywords
Content
ARM Cortex-M0, LPC1111, LPC1112, LPC1113, LPC1114, LPC1115,
LPC11C12, LPC11C14, LPC1100, LPC1100L, LPC11C00, LPC11C22,
LPC11C24, LPC11D14, LPC1100XL
LPC111x/LPC11Cxx User manual
Abstract
NXP Semiconductors
UM10398
LPC111x/LPC11Cxx User manual
Revision history
Rev
12.1
Modifications:
Date
20130807
Description
LPC111x/LPC11C1x/LPC11C2x User manual
•
•
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•
•
•
•
•
•
•
•
•
•
•
Remove instruction breakpoints from feature list for SWD. See
Section 27.2.
IRQLATENCY register added in SYSCON block. See
Table 35.
Reset value of the C_CAN CANCLKDIV register changed to 0x1, See
Table 275.
RAM used by ISP sizes updated. See
Section 26.4.8, Section 26.4.9.
SSEL1_LOC Register description corrected. See
Table 152.
Added LPC1115FET48.
Editorial updates.
Updated Go command
Section 26.5.8.
LPC111x/LPC11C1x/LPC11C2x User manual
BOD level 0 for reset added. See
Table 33.
Description of the TEMT bit in the UART LSR register updated. See
Table 196.
LPC111x/LPC11C1x/LPC11C2x User manual
Function SSEL1 added to pin PIO2_0 in Table 170 and Figure 28.
BOD level 0 for reset and interrupt removed.
LPC111x/LPC11C1x/LPC11C2x User manual
LPC1112FHN24 pinout corrected in Table 161 and Figure 18.
Description of BYPASS bit corrected in Table 12 “System oscillator control register (SYSOSCCTRL,
address 0x4004 8020) bit description”.
LPC111x/LPC11C1x/LPC11C2x/LPC11D14 User manual
LPC11D14/PCF8576D block diagram updated (see Figure 5).
Description of interrupt use with IAP calls updated (see Section 26.4.7).
SYSRSTSTAT register access changed to R/W (Table 7).
Frequency values for FREQSEL bits in the WDTOSCCTRL register corrected (see Table 13).
Figure 9 updated (RESET changed to internal reset).
Limit number of bytes copied in Copy RAM to flash ISP and IAP commands for parts with less than
4 kB SRAM (see Table 381 and Table 396).
Figure 14 updated with pseudo open-drain mode.
Part LPC1112FHN24/202 added.
Part IDs added for parts LPC1110FD20, LPC1111FDH20/002, LPC1112FD20/102,
LPC1112FDH20/102, LPC1112FDH28/102, LPC1114FDH28/102, LPC1114FN28/102.
SRAM use by bootloader specified in Section 26.3.1.
LPC111x/LPC11C1x/LPC11C2x User manual
LPC111x/LPC11C1x/LPC11C2x User manual
LPC111x/LPC11C1x/LPC11C2x User manual
LPC111x/LPC11C1x/LPC11C2x User manual
12
Modifications:
11
Modifications:
10
Modifications:
20120924
20120726
20120626
9
Modifications:
20120517
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•
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8
7
6
5
20120308
20110919
20110822
20110621
Contact information
For more information, please visit:
http://www.nxp.com
For sales office addresses, please send an email to:
salesaddresses@nxp.com
UM10398
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
User manual
Rev. 12.1 — 7 August 2013
2 of 543
NXP Semiconductors
UM10398
Chapter :
Revision history
…continued
Rev
4
3
2
1
Date
20110304
20110114
20101102
20100721
Description
LPC111x/LPC11C1x/LPC11C2x User manual
LPC111x/LPC11C1x/LPC11C2x User manual
LPC111x/LPC11C1x User manual
LPC111x/LPC11C1x User manual
UM10398
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
User manual
Rev. 12.1 — 7 August 2013
3 of 543
UM10398
Chapter 1: LPC111x/LPC11Cxx Introductory information
Rev. 12.1 — 7 August 2013
User manual
1.1 Introduction
The LPC111x/LPC11Cxx are a ARM Cortex-M0 based, low-cost 32-bit MCU family,
designed for 8/16-bit microcontroller applications, offering performance, low power, simple
instruction set and memory addressing together with reduced code size compared to
existing 8/16-bit architectures.
The LPC111x/LPC11Cxx operate at CPU frequencies of up to 50 MHz.
The peripheral complement of the LPC111x/LPC11Cxx includes up to 32 kB of flash
memory, up to 8 kB of data memory, one C_CAN controller (LPC11Cxx), one Fast-mode
Plus I
2
C-bus interface, one RS-485/EIA-485 UART, up to two SPI interfaces with SSP
features, four general purpose timers, a 10-bit ADC, and up to 42 general purpose I/O
pins.
On-chip C_CAN drivers and flash In-System Programming tools via C_CAN are included
on the LPC11Cxx. In addition, parts LPC11C2x are equipped with an on-chip CAN
transceiver.
Remark:
This user manual covers the LPC111x/LPC11Cxx parts and the LPC11D14
dual-chip part with PCF8576D LCD controller. The LPC111x/LPC11Cxx parts are grouped
by the following series and part names (see
Table 1
for a feature overview):
•
LPC1100 series (parts LPC111x/101/201/301)
•
LPC1100L series (parts LPC111x/102/202/302) and part LPC11D14 with LCD
controller.
•
LPC1100XL series (parts LPC111x/103/203/323/333)
•
LPC11C00 series (parts LPC11C1x/301 and LPC11C2x/301) with C_CAN controller.
UM10398
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
User manual
Rev. 12.1 — 7 August 2013
1 of 543
NXP Semiconductors
UM10398
Chapter 1: LPC111x/LPC11Cxx Introductory information
LPC111x/LPC11Cxx feature changes
Features overview
Table 1.
Series
LPC1100 series
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•
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•
•
I2C, SSP, UART, GPIO
Timers and watch dog timer
10-bit ADC
Flash/SRAM memory
For a full feature list, see
Section 1.2.
LPC1100L series
LPC1100 series features plus the following additional features:
•
Power profiles with lower power consumption in Active and Sleep modes.
•
Internal pull-up resistors pull up pins to full V
DD
level.
•
Programmable pseudo open-drain mode for GPIO pins.
•
WWDT with clock source lock capability.
•
Small packages (TSSOP, SO, DIP, HVQFN)
LPC1100XL
series
LPC1100L series features plus the following new features:
•
•
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•
•
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Flash page erase In-Application Programming (IAP) function.
Timer, UART, and SSP functions pinned out on additional pins.
One capture function added for each timer.
Capture-clear feature on the 16-bit and 32-bit timers for easy pulse-width
measurements.
CAN controller.
On-chip CAN drivers.
On-chip CAN transceiver (LPC11C2x).
WDT (not windowed) with clock source lock capability.
LPC11C00 series
LPC1100 series features plus the following additional features:
LPC11D14
(LPC1100L
series)
LPC1100L series with LCD controller PCF8576D in a dual-chip package.
UM10398
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
User manual
Rev. 12.1 — 7 August 2013
2 of 543
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