LXT381LE datasheet, PDF - EEWORLD Datasheet

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LXT381LE: DescriptionPCM Transceiver, 1-Func, PQFP144, LQFP-144; CategoryWireless rf/communication Telecom circuit; File Size504KB，36 Pages; ManufacturerCortina Systems Inc

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LXT381LE Overview

PCM Transceiver, 1-Func, PQFP144, LQFP-144

LXT381LE Parametric

Parameter Name	Attribute value
Maker	Cortina Systems Inc
Parts packaging code	QFP
package instruction	LFQFP,
Contacts	144
Reach Compliance Code	compli
JESD-30 code	S-PQFP-G144
length	20 mm
Number of functions	1
Number of terminals	144
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Certification status	Not Qualified
Maximum seat height	1.6 mm
Nominal supply voltage	3.3 V
surface mount	YES
Telecom integrated circuit types	PCM TRANSCEIVER
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
width	20 mm

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LXT381

Octal E1 Line Interface Unit

Datasheet

General Description

The LXT381 is an octal short haul analog Line Interface Unit for ITU G.703 2.048 Mbit/sec.

transmission systems. It incorporates eight independent receivers and eight independent

transmitters in a single LQFP-144 or PBGA-160 package.

The transmit output drivers provide low impedance, constant during marks and spaces and

constant pulse amplitudes independent of supply voltage variations.

The LXT381 may be configured for unbalanced 75

Ω

or for balanced 120

Ω

systems without

external component changes in the transmit section. The transmit return loss performance

exceeds latest ETSI return loss recommendations such as ETS 300166.

The LXT381 features a differential data receiver architecture with high noise interference

margin. The receivers use peak detection and a variable threshold for reliable data recovery

down to 500 mV or up to 12 dB of cable attenuation.

Each receiver incorporates an analog Loss Of Signal (LOS) processor that meets latest ITU

G.775 standard.

The fast power down mode of all transmitters allows the implementation of Hitless Protection

Switching (HPS) application without the use of relays.

Applications

Synchronous Digital Hierarchy

(SDH) E1 tributary interfaces

Public switching trunk line interfaces

Digital Access Cross Connects (DACS)

Microwave transmission systems

Product Features

Octal E1 short haul line interface per ITU

G.703

Single rail supply voltage of 3.3V with 5V

I/O capability

Low power consumption of <100 mW per

channel (typ.)

Ω

/120

Ω

TX operation without

component changes

Transmit return loss complies with ETSI

ETS 300 166

Hitless Protection Switching (HPS)

Driver short circuit current limiter (<50 mA

RMS)

Differential receiver with 15dB of signal to

noise interference margin

Data recovery with no need for external

reference clock

Analog LOS detection per ITU G.775

Simple hardware control mode

JTAG Boundary Scan test port per IEEE

1149.4

Small footprint 144 pin LQFP or 160 pin

PBGA package

As of January 15, 2001, this document replaces the Level One document

known as

Octal E1 Line Interface.

Order Number: 249005-001

January 2001

Octal E1 Line Interface Unit — LXT381

Contents

1.0

2.0

Pin Assignments and Signal Descriptions

...................................................... 5

Functional Description

...........................................................................................13

2.1

2.2

2.3

2.4

2.5

Receiver ..............................................................................................................13

2.1.1 Loss Of Signal Detector .........................................................................13

Transmitter ..........................................................................................................13

2.2.1 Transmit Pulse Shaping .........................................................................14

Interfacing with 5V logic ......................................................................................14

Line Protection ....................................................................................................14

Loopbacks ...........................................................................................................14

2.5.1 Analog Loopback....................................................................................15

2.5.2 Remote Loopback ..................................................................................15

Hitless Protection Switching (HPS) .....................................................................15

Overview .............................................................................................................18

Architecture .........................................................................................................18

3.2.1 TAP Controller........................................................................................19

JTAG Register Description..................................................................................20

3.3.1 Boundary Scan Register (BSR)..............................................................21

3.3.2 Device Identification Register (IDR) .......................................................24

3.3.3 Bypass Register (BYR) ..........................................................................24

3.3.4 Analog Port Scan Register (ASR) ..........................................................24

3.3.5 Instruction Register (IR) .........................................................................25

2.6

3.0

JTAG Boundary Scan

.............................................................................................18

3.1

3.2

3.3

4.0

5.0

Test Specifications

..................................................................................................27

Mechanical Specifications

....................................................................................34

Datasheet

LXT381 — Octal E1 Line Interface Unit

Figures

LXT381 144-Pin Low-Profile Quad Flat Package (LQFP) Pin Assignments and

Package Markings5

LXT381 160-Pin Plastic Ball Grid Array (PBGA) Pin Assignments ....................... 6

Analog Loopback ................................................................................................ 15

Remote Looback ................................................................................................. 15

External Transmit/Receive Line Circuitry ........................................................... 17

LXT381 JTAG Architecture ................................................................................. 18

JTAG State Diagram ........................................................................................... 20

Analog Test Port Application.............................................................................. 26

Transmit Clock Timing ........................................................................................ 30

Receive Timing Diagram..................................................................................... 31

JTAG Timing ....................................................................................................... 31

E1 Mask Templates ............................................................................................ 33

LXT381 144 Pin LQFP Package Dimensions ..................................................... 34

LXT381 160 Pin PBGA Package Dimensions..................................................... 35

Tables

LXT381 Pin Description ........................................................................................ 7

Operation Mode Summary .................................................................................. 16

TAP State Description......................................................................................... 19

Boundary Scan Register (BSR) .......................................................................... 21

Device Identification Register (IDR) .................................................................... 24

Analog Port Scan Register (ASR) ....................................................................... 24

Instruction Register (IR) ...................................................................................... 26

Absolute Maximum Ratings ................................................................................ 27

Recommended Operating Conditions ................................................................. 27

Transmit Transmission Characteristics ............................................................... 28

DC Characteristics .............................................................................................. 28

Receive Transmission Characteristics ................................................................ 29

Analog Test Port Characteristics......................................................................... 30

Transmit Timing Characteristics.......................................................................... 30

Receive Timing Characteristics........................................................................... 30

JTAG Timing Characteristics .............................................................................. 31

Transformer Specifications ................................................................................. 32

G.703 2.048 Mbit/s Pulse Mask Specifications ................................................... 32

Datasheet

LXT381LE Related Products

	LXT381LE	DJLXT381LE.B4	LXT381BE
Description	PCM Transceiver, 1-Func, PQFP144, LQFP-144	Telecom IC, PQFP144,	PCM Transceiver, 1-Func, PBGA160, PLASTIC, BGA-160
Maker	Cortina Systems Inc	Cortina Systems Inc	Cortina Systems Inc
package instruction	LFQFP,	QFP, QFP144,.87SQ,20	BGA,
Reach Compliance Code	compli	unknown	compliant
JESD-30 code	S-PQFP-G144	S-PQFP-G144	S-PBGA-B160
Number of terminals	144	144	160
Minimum operating temperature	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LFQFP	QFP	BGA
Package shape	SQUARE	SQUARE	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK	GRID ARRAY
Certification status	Not Qualified	Not Qualified	Not Qualified
Nominal supply voltage	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES
Terminal form	GULL WING	GULL WING	BALL
Terminal pitch	0.5 mm	0.5 mm	1 mm
Terminal location	QUAD	QUAD	BOTTOM
Parts packaging code	QFP	-	BGA
Contacts	144	-	160
length	20 mm	-	15 mm
Number of functions	1	-	1
Maximum operating temperature	85 °C	-	85 °C
Maximum seat height	1.6 mm	-	1.8 mm
Telecom integrated circuit types	PCM TRANSCEIVER	-	PCM TRANSCEIVER
Temperature level	INDUSTRIAL	-	INDUSTRIAL
width	20 mm	-	15 mm

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