High Speed Super Low Power SRAM
512k Word By 16 bit
CS16LV81923
Revision History
Rev. No.
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
History
Initial issue with new naming rule
Add 48CSP-6x8mm package outline
Revise 48CSP-8x10mm pkg code from W to K
Revised DC characteristics
Revised DC characteristics
Change wafer process from 0.18um to 0.15um
Add CE2 description of 48BGA package
Modify Data Retention waveform
Issue Date
Feb.15, 2005
Mar. 08, 2005
Oct. 25, 2005
Nov. 23, 2006
Jun. 20,2007
May. 19, 2008
Nov. 20, 2009
May. 27.2010
1
Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
512k Word By 16 bit
CS16LV81923
PRODUCT DESCRIPTION
The CS16LV81923 is a high performance, high speed, low power CMOS Static Random
Access Memory organized as 524,288 words by 16 bits and operates from a wide range of 2.7 to
3.6V supply voltage. Advanced 0.15um CMOS technology and circuit techniques provide both high
speed and low power features with a Typical CMOS standby current of 0.3uA and maximum access
time of 55/70ns in 3.0V operation. Easy memory expansion is provided by an active LOW chip
enable1 (/CE), active HIGH chip enable2 (CE2) for BGA product and active LOW output enable
(/OE) and three-state output drivers.
The CS16LV81923 has an automatic power down feature, reducing the power consumption
significantly when chip is deselected. The CS16LV81923 is available in JEDEC standard 44L TSOP
2 and 48Ball Mini_BGA 8x10mm packages.
FEATURES
Low operation voltage: 2.7 ~ 3.6V
Ultra low power consumption:
Vcc = 3.0V: 25mA (Typ.) operating current, 0.3uA (Typ.) CMOS standby current
High speed access time: 55/70ns (Max.) at Vcc = 3.0V.
Automatic power down when chip is deselected.
Three state outputs and TTL compatible.
Data retention supply voltage as low as 1.5V.
Easy expansion with /CE&CE2 and /OE options.
PRODUCT FAMILY
Product Family
Operating
Temp
Vcc. Range
Speed (ns)
Standby
Current
(Typ.)
0.3 uA
(V
CC
= 3.0V)
2.7 ~ 3.6
-40 ~ 85
o
C
55/70
0.3 uA
(V
CC
= 3.0V)
44 TSOP 2-400mil
48 Mini_BGA 8x10mm
Package Type
0 ~ 70
o
C
CS16LV81923
2
Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
512k Word By 16 bit
CS16LV81923
PIN CONFIGURATIONS
■
FUNCTIONAL BLOCK DIAGRAM
For single CE product of 44 TSOP 2-400mil
3
Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
512k Word By 16 bit
CS16LV81923
For dual CE product of 48 Mini_BGA 8x10mm
PIN DESCRIPTIONS
Name
A0 ~ A18
/CE
/CE1 & CE2
Type
Input
Function
19 address inputs for selecting one of the 524,288 x 16 bit words in the RAM
/CE1 is active LOW and CE2 is active high. Chip enable must be active when
Input
data read from or write to the device. If chip enable is not active, the device is
deselected and in a standby power mode. The DQ pins will be in high
impedance state when the device is deselected.
The Write enable input is active LOW. It controls read and write operations.
/WE
Input
With the chip selected, when /WE is HIGH and /OE is LOW, output data will be
present on the DQ pins, when /WE is LOW, the data present on the DQ pins
will be written into the selected memory location.
The output enable input is active LOW. If the output enable is active while the
/OE
Input
chip is selected and the write enable is inactive, data will be present on the DQ
pins and they will be enabled. The DQ pins will be in the high impedance state
when /OE is inactive.
/LB and /UB
DQ0~DQ15
Vcc
Vss
Input
I/O
Power
Power
Lower byte and upper byte data input/output control pins.
These 16 bi-directional ports are used to read data from or write data into the
RAM.
Power Supply
Ground
4
Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
512k Word By 16 bit
TRUTH TABLE
MODE
Fully
Standby
Output
L
Disabled
L
Read
L
L
H
H
L
H
L
L
Write
L
L
H
L
X
H
L
L
L
H
L
L
H
D
OUT
High Z
D
OUT
D
IN
High Z
D
IN
D
OUT
D
OUT
High Z
D
IN
D
IN
High-Z
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
L
H
H
H
X
X
High Z
High Z
I
CC
/CE
H
X
(1)
CS16LV81923
/CE1
H
X
(2)
CE2
X
L
(2)
/WE
X
X
/OE
X
X
/LB
X
X
/UB
X
X
DQ0~7
High Z
High Z
DQ8~15
High Z
High Z
Vcc Current
I
CCSB
, I
CCSB1
I
CCSB
, I
CCSB1
Note: (1) /CE is used for 44 TSOP 2-400mil of single CE product only.
(2) /CE1 and CE2 are used for 48 Mini_BGA 8x10mm dual CE product only.
ABSOLUTE MAXIMUM RATINGS
Symbol
V
TERM
T
BIAS
T
STG
P
T
I
OUT
(1)
Parameter
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Rating
-0.2 to Vcc+0.5
-40 to +125
-60 to +150
1.0
35
Unit
V
O
C
C
O
W
mA
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
5
Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
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