CS18LV10245DC-70 datasheet, PDF

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CS18LV10245DC-70: DescriptionStandard SRAM, 128KX8, 70ns, CMOS, PDSO32, 8 X 13.40 MM, STSOP1-32; Categorystorage storage; File Size844KB，18 Pages; ManufacturerChiplus Semiconductor Corp

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CS18LV10245DC-70 Overview

Standard SRAM, 128KX8, 70ns, CMOS, PDSO32, 8 X 13.40 MM, STSOP1-32

CS18LV10245DC-70 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Chiplus Semiconductor Corp
package instruction	8 X 13.40 MM, STSOP1-32
Reach Compliance Code	unknow
ECCN code	EAR99
Maximum access time	70 ns
I/O type	COMMON
JESD-30 code	R-PDSO-G32
JESD-609 code	e0
length	11.8 mm
memory density	1048576 bi
Memory IC Type	STANDARD SRAM
memory width	8
Humidity sensitivity level	3
Number of functions	1
Number of terminals	32
word count	131072 words
character code	128000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128KX8
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP1
Encapsulate equivalent code	TSSOP32,.56,20
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Parallel/Serial	PARALLEL
power supply	5 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum standby current	0.000005 A
Minimum standby current	2 V
Maximum slew rate	0.03 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
width	8 mm

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High Speed Super Low Power SRAM

128K Word By 8 Bit

CS18LV10245

Revision History

Rev. No.

1.0

1.1

1.2

1.3

History

New Issue

Add a new 32L WSON-8x8mm package

Revise I

CCSB1

Typ

Remove WSON

Issue Date

Jun.29, 2005

Aug.12, 2005

Apr. 07,2006

June.12.2006

Remark

Rev. 1.3

Chiplus reserves the right to change product or specification without notice.

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