pASIC 3 FPGA Family Data Sheet
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Up to 60,000 Usable PLD Gate pASIC 3 FPGA Combining High
Performance and High Density
Device Highlights
High Performance & High Density
• Up to 60,000 usable PLD gates with up to
316 I/Os
• 300 MHz 16-bit counters, 400 MHz datapaths
• 0.35 µm four-layer metal non-volatile CMOS
process for smallest die sizes
Up to Eight Low-Skew Distributed
Networks
• Two array clock/control networks are available to
the logic cell flip-flop; clock, set, and reset inputs
— each can be driven by an input-only pin
• Up to six global clock/control networks are
available to the logic cell; F1, clock, set, and reset
inputs and the data input, I/O register clock,
reset, and enable inputs as well as the output
enable control — each can be driven by an input-
only pin, I/O pin, any logic cell output, or I/O cell
feedback
Easy to Use/Fast Development
Cycles
• 100% routable with 100% utilization and
complete pin-out stability
• Variable-grain logic cells provide high
performance and 100% utilization
• Comprehensive design tools include high quality
Verilog/VHDL synthesis
High Performance
• Input + logic cell + output total delays under 6 ns
• Data path speeds over 400 MHz
• Counter speeds over 300 MHz
Figure 1:
Up to 1,584
pASIC 3 Logic Cells
Advanced I/O Capabilities
• Interfaces with 3.3 V and 5.0 V devices
• PCI compliant with 3.3 V and 5.0 V buses
for -1/-2/-3/-4 speed grades
• Full JTAG boundary scan
• I/O cells with individually controlled registered
input path and output enables
Up to 316 I/O Pins
• Up to 308 bidirectional input/output pins,
PCI-compliant for 5.0 V and 3.3 V buses for
-1/-2/-3/-4 speed grades
• Up to eight high-drive input/distributed network
pins
© 2005 QuickLogic Corporation
www.quicklogic.com
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pASIC 3 FPGA Family Data Sheet Rev. D
Table 1: pASIC 3 Product Family Members
QL3004
Max Gates
Logic Array
Logic Cells
Max Flip-Flops
Max I/O
PLCC
PLCC
TQFP
Packages
TQFP
PQFP
PBGA
PBGA
5,188
8 x 12
96
178
74
68
84
100
-
-
-
-
QL3004E
5,188
8 x 12
96
178
74
68
84
100
-
-
-
-
QL3006
8,008
10 x 16
160
322
74
68
84
100
-
-
-
-
QL3012
15,740
20 x 16
320
438
110
-
84
100
144
-
-
-
QL3025
32,616
28 x 24
672
876
196
-
-
100
144
208
256
-
QL3040
48,384
36 x 28
1,008
1,260
244
-
-
-
-
208
-
456
QL3060
75,232
44 x 36
1,584
1,900
308
-
-
-
-
208
-
456
Table 2: Max I/O per Device/Package Combination
Device
QL3004
QL3004E
QL3006
QL3012
QL3025
QL3040
QL3060
68 PLCC
46
46
46
-
-
-
-
84 PLCC
60
60
60
60
-
-
-
100 TQFP
74
74
74
74
74
-
-
144 TQFP
-
-
-
110
110
-
-
208 PQFP
-
-
-
-
166
166
166
256PBGA
-
-
-
-
196
-
-
456 PBGA
-
-
-
-
-
244
308
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© 2005 QuickLogic Corporation
pASIC 3 FPGA Family Data Sheet Rev. D
Architecture Overview
The pASIC 3 family of devices have a range of 4,000 to 60,000 usable PLD gates. pASIC 3 FPGAs are
fabricated on a 0.35 µm four-layer metal process using QuickLogic’s“ patented ViaLink“ technology to provide
a unique combination of high performance, high density, low cost, and extreme ease-of-use.
The pASIC 3 family of devices contain a range of 96 to 1,584 logic cells (see
Table 1).
With a range of 74 to
316 I/Os, the pASIC 3 family is available in many device/package combinations (see
Table 2).
Software support for the complete pASIC 3 family is available through two basic packages. The turnkey
QuickWorks
package provides the most complete FPGA software solution from design entry to logic
synthesis, to place and route, to simulation. The QuickTools
TM
for Workstations package provides a solution
for designers who use Cadence
, Exemplar
TM
, Mentor
, Synopsys
, Synplicity
, Viewlogic
TM
, Aldec
TM
, or
other third-party tools for design entry, synthesis, or simulation.
© 2005 QuickLogic Corporation
www.quicklogic.com
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pASIC 3 FPGA Family Data Sheet Rev. D
Electrical Specifications
AC Characteristics at V
CC
= 3.3 V, TA = 25°C (K = 1.00)
To calculate delays, multiply the appropriate K factor from
Table 9
by the numbers provided in
Table 3
through
Table 7.
Table 3: Logic Cells
Symbol
t
PD
t
SU
t
H
t
CLK
t
CWHI
t
CWLO
t
SET
t
RESET
t
SW
t
RW
Parameter
Combinatorial Delay
b
Setup Time
b
Hold Time
Clock to Q Delay
Clock High Time
Clock Low Time
Set Delay
Reset Delay
Set Width
Reset Width
Propagation Delays (ns) Fanout
a
1
1.4
1.7
0.0
0.7
1.2
1.2
1.0
0.8
1.9
1.8
2
1.7
1.7
0.0
1.0
1.2
1.2
1.3
1.1
1.9
1.8
3
1.9
1.7
0.0
1.2
1.2
1.2
1.5
1.3
1.9
1.8
4
2.2
1.7
0.0
1.5
1.2
1.2
1.8
1.6
1.9
1.8
8
3.2
1.7
0.0
2.5
1.2
1.2
2.8
2.6
1.9
1.8
a. Stated timing for worst case Propagation Delay over process variation at V
CC
= 3.3 V and TA = 25
°
C. Multiply by the appropriate
Delay Factor, K, for speed grade, voltage, and temperature settings as specified in
Table 9
.
b. These limits are derived from a representative selection of the slowest paths through the pASIC 3 logic cell including typical net
delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design.
Table 4: Input-Only/Clock Cells
Symbol
t
IN
t
INI
t
ISU
t
IH
t
lCLK
t
lRST
t
lESU
t
lEH
Parameter
High Drive Input Delay
High Drive Input, Inverting Delay
Input Register Set-Up Time
Input Register Hold Time
Input Register Clock To Q
Input Register Reset Delay
Input Register clock Enable Set-Up Time
Input Register Clock Enable Hold Time
Propagation Delays (ns) Fanout
a
1
1.5
1.6
3.1
0.0
0.7
0.6
2.3
0.0
2
1.6
1.7
3.1
0.0
0.8
0.7
2.3
0.0
3
1.8
1.9
3.1
0.0
1.0
0.9
2.3
0.0
4
1.9
2.0
3.1
0.0
1.1
1.0
2.3
0.0
8
2.4
2.5
3.1
0.0
1.6
1.5
2.3
0.0
12
2.9
3.0
3.1
0.0
2.1
2.0
2.3
0.0
24
4.4
4.5
3.1
0.0
3.6
3.5
2.3
0.0
a. Stated timing for worst case Propagation Delay over process variation at V
CC
= 3.3 V and TA = 25
°
C. Multiply by the appropriate
Delay Factor, K, for speed grade, voltage, and temperature settings as specified in
Table 9
.
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© 2005 QuickLogic Corporation
pASIC 3 FPGA Family Data Sheet Rev. D
Table 5: Clock Cells
Symbol
t
ACK
t
GCKP
t
GCKB
Parameter
Array Clock Delay
Global Clock Pin Delay
Global Clock Buffer Delay
Propagation Delays (ns) Loads per Half Column
a
1
1.2
0.7
0.8
2
1.2
0.7
0.8
3
1.3
0.7
0.9
4
1.3
0.7
0.9
8
1.5
0.7
1.1
10
1.6
0.7
1.2
11
1.7
0.7
1.3
a. The array distributed networks consist of 40 half columns and the global distributed networks consist of 44 half columns, each driven
by an independent buffer. The number of half columns used does not affect clock buffer delay. The array clock has up to eight loads
per half column. The global clock has up to 11 loads per half column.
Table 6: Input-Only I/O Cells
Symbol
t
I/O
t
ISU
t
IH
t
lOCLK
t
lORST
t
lESU
t
lEH
Parameter
Input Delay (bidirectional pad)
Input Register Set-Up Time
Input Register Hold Time
Input Register Clock To Q
Input Register Reset Delay
Input Register clock Enable Set-Up Time
Input Register Clock Enable Hold Time
Propagation Delays (ns) Fanout
a
1
1.3
3.1
0.0
0.7
0.6
2.3
0.0
2
1.6
3.1
0.0
1.0
0.9
2.3
0.0
3
1.8
3.1
0.0
1.2
1.1
2.3
0.0
4
2.1
3.1
0.0
1.5
1.4
2.3
0.0
8
3.1
3.1
0.0
2.5
2.4
2.3
0.0
10
3.6
3.1
0.0
3.0
2.9
2.3
0.0
a. Stated timing for worst case Propagation Delay over process variation at V
CC
= 3.3 V and TA = 25
°
C. Multiply by the appropriate
Delay Factor, K, for speed grade, voltage, and temperature settings as specified in
Table 9
.
Table 7: Output-Only I/O Cells
Symbol
t
OUTLH
t
OUTHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Parameter
Output Delay Low to High
Output Delay High to Low
Output Delay Tri-state to High
Output Delay Tri-state to Low
Output Delay High to Tri-State
a
Output Delay Low to Tri-State
Propagation Delays (ns) Output Load Capacitance (pF)
30
2.1
2.2
1.2
1.6
2.0
1.2
50
2.5
2.6
1.7
2.0
-
-
75
3.1
3.2
2.2
2.6
-
-
100
3.6
3.7
2.8
3.1
-
-
150
4.7
4.8
3.9
4.2
-
-
a. The loads presented in
Figure
2
are used for t
PXZ
:
Figure 2: Loads used for t
PXZ
t
PHZ
1ΚΩ
5 pF
1ΚΩ
t
PLZ
5 pF
© 2005 QuickLogic Corporation
www.quicklogic.com
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