PR ELIMIN ARY
LM3S6730 Microcontroller
DATA SHE ET
DS-LM3S6730- 4 28 3
Copyrig ht
©
2007-2008 Luminary Micro, Inc.
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©
2007-2008 Luminary Micro, Inc. All rights reserved. Stellaris, Luminary Micro, and the Luminary Micro logo are registered trademarks of
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LM3S6730 Microcontroller
Table of Contents
Revision History ............................................................................................................................. 16
About This Document .................................................................................................................... 18
Audience ..............................................................................................................................................
About This Manual ................................................................................................................................
Related Documents ...............................................................................................................................
Documentation Conventions ..................................................................................................................
18
18
18
18
21
27
27
29
29
29
30
30
31
32
33
33
35
35
35
36
36
36
36
36
1
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
1.4.8
Architectural Overview ...................................................................................................... 21
Product Features ......................................................................................................................
Target Applications ....................................................................................................................
High-Level Block Diagram .........................................................................................................
Functional Overview ..................................................................................................................
ARM Cortex™-M3 .....................................................................................................................
Motor Control Peripherals ..........................................................................................................
Analog Peripherals ....................................................................................................................
Serial Communications Peripherals ............................................................................................
System Peripherals ...................................................................................................................
Memory Peripherals ..................................................................................................................
Additional Features ...................................................................................................................
Hardware Details ......................................................................................................................
Block Diagram ..........................................................................................................................
Functional Description ...............................................................................................................
Serial Wire and JTAG Debug .....................................................................................................
Embedded Trace Macrocell (ETM) .............................................................................................
Trace Port Interface Unit (TPIU) .................................................................................................
ROM Table ...............................................................................................................................
Memory Protection Unit (MPU) ...................................................................................................
Nested Vectored Interrupt Controller (NVIC) ................................................................................
2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
ARM Cortex-M3 Processor Core ...................................................................................... 34
3
4
5
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.3
5.4
5.4.1
5.4.2
Memory Map ....................................................................................................................... 40
Interrupts ............................................................................................................................ 42
JTAG Interface .................................................................................................................... 45
Block Diagram ..........................................................................................................................
Functional Description ...............................................................................................................
JTAG Interface Pins ..................................................................................................................
JTAG TAP Controller .................................................................................................................
Shift Registers ..........................................................................................................................
Operational Considerations ........................................................................................................
Initialization and Configuration ...................................................................................................
Register Descriptions ................................................................................................................
Instruction Register (IR) .............................................................................................................
Data Registers ..........................................................................................................................
46
46
46
48
49
49
52
52
52
54
6
6.1
6.1.1
System Control ................................................................................................................... 57
Functional Description ............................................................................................................... 57
Device Identification .................................................................................................................. 57
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Table of Contents
6.1.2
6.1.3
6.1.4
6.1.5
6.2
6.3
6.4
Reset Control ............................................................................................................................
Power Control ...........................................................................................................................
Clock Control ............................................................................................................................
System Control .........................................................................................................................
Initialization and Configuration ...................................................................................................
Register Map ............................................................................................................................
Register Descriptions ................................................................................................................
57
60
61
64
65
66
67
7
7.1
7.2
7.2.1
7.2.2
7.3
7.3.1
7.3.2
7.4
7.5
7.6
Internal Memory ............................................................................................................... 114
Block Diagram ........................................................................................................................ 114
Functional Description ............................................................................................................. 114
SRAM Memory ........................................................................................................................ 114
Flash Memory ......................................................................................................................... 115
Flash Memory Initialization and Configuration ........................................................................... 116
Flash Programming ................................................................................................................. 116
Nonvolatile Register Programming ........................................................................................... 116
Register Map .......................................................................................................................... 117
Flash Register Descriptions (Flash Control Offset) ..................................................................... 118
Flash Register Descriptions (System Control Offset) .................................................................. 125
8
8.1
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.1.6
8.2
8.3
8.4
General-Purpose Input/Outputs (GPIOs) ....................................................................... 138
Functional Description ............................................................................................................. 138
Data Control ........................................................................................................................... 139
Interrupt Control ...................................................................................................................... 140
Mode Control .......................................................................................................................... 141
Commit Control ....................................................................................................................... 141
Pad Control ............................................................................................................................. 141
Identification ........................................................................................................................... 141
Initialization and Configuration ................................................................................................. 141
Register Map .......................................................................................................................... 142
Register Descriptions .............................................................................................................. 144
9
9.1
9.2
9.2.1
9.2.2
9.2.3
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.4
9.5
General-Purpose Timers ................................................................................................. 179
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
GPTM Reset Conditions ..........................................................................................................
32-Bit Timer Operating Modes ..................................................................................................
16-Bit Timer Operating Modes ..................................................................................................
Initialization and Configuration .................................................................................................
32-Bit One-Shot/Periodic Timer Mode .......................................................................................
32-Bit Real-Time Clock (RTC) Mode .........................................................................................
16-Bit One-Shot/Periodic Timer Mode .......................................................................................
16-Bit Input Edge Count Mode .................................................................................................
16-Bit Input Edge Timing Mode ................................................................................................
16-Bit PWM Mode ...................................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
179
180
181
181
182
186
186
187
187
188
188
189
189
190
10
10.1
10.2
Watchdog Timer ............................................................................................................... 215
Block Diagram ........................................................................................................................ 216
Functional Description ............................................................................................................. 216
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LM3S6730 Microcontroller
10.3
10.4
10.5
Initialization and Configuration ................................................................................................. 217
Register Map .......................................................................................................................... 217
Register Descriptions .............................................................................................................. 218
11
11.1
11.2
11.2.1
11.2.2
11.2.3
11.2.4
11.2.5
11.2.6
11.2.7
11.2.8
11.3
11.4
11.5
Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 239
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Transmit/Receive Logic ...........................................................................................................
Baud-Rate Generation .............................................................................................................
Data Transmission ..................................................................................................................
Serial IR (SIR) .........................................................................................................................
FIFO Operation .......................................................................................................................
Interrupts ................................................................................................................................
Loopback Operation ................................................................................................................
IrDA SIR block ........................................................................................................................
Initialization and Configuration .................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Bit Rate Generation .................................................................................................................
FIFO Operation .......................................................................................................................
Interrupts ................................................................................................................................
Frame Formats .......................................................................................................................
Initialization and Configuration .................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
240
240
240
241
242
242
243
243
244
244
244
245
246
280
280
281
281
281
282
289
290
291
12
12.1
12.2
12.2.1
12.2.2
12.2.3
12.2.4
12.3
12.4
12.5
Synchronous Serial Interface (SSI) ................................................................................ 280
13
13.1
13.2
13.2.1
13.2.2
13.2.3
13.2.4
13.3
13.4
13.5
13.6
Ethernet Controller .......................................................................................................... 317
Block Diagram ........................................................................................................................ 317
Functional Description ............................................................................................................. 318
MAC Operation ....................................................................................................................... 318
Internal MII Operation .............................................................................................................. 322
PHY Operation ........................................................................................................................ 322
Interrupts ................................................................................................................................ 323
Initialization and Configuration ................................................................................................. 323
Ethernet Register Map ............................................................................................................. 324
Ethernet MAC Register Descriptions ......................................................................................... 325
MII Management Register Descriptions ..................................................................................... 343
14
14.1
14.2
14.2.1
14.3
14.4
14.5
Analog Comparators ....................................................................................................... 362
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Internal Reference Programming ..............................................................................................
Initialization and Configuration .................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
362
363
363
364
365
365
November 16, 2008
Preliminary
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Power technology
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