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PDM41532SA12SOTR

Description
Standard SRAM, 128KX8, 12ns, CMOS, PDSO44
Categorystorage    storage   
File Size369KB,10 Pages
ManufacturerParadigm Technology Inc
Download Datasheet Parametric View All

PDM41532SA12SOTR Overview

Standard SRAM, 128KX8, 12ns, CMOS, PDSO44

PDM41532SA12SOTR Parametric

Parameter NameAttribute value
MakerParadigm Technology Inc
package instruction,
Reach Compliance Codeunknow
ECCN code3A991.B.2.B
Maximum access time12 ns
JESD-30 codeR-PDSO-J44
memory density1048576 bi
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of ports1
Number of terminals44
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize128KX8
Output characteristics3-STATE
ExportableYES
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
Certification statusNot Qualified
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formJ BEND
Terminal locationDUAL
PRELIMINARY
PDM41532
64K x 16 CMOS
Static RAM
Features
n
Description
The PDM41532 is a high-performance CMOS static
RAM organized as 65,536 x 16 bits. The PDM41532
features low power dissipation using chip enable
(CE) and has an output enable input (OE) for fast
memory access. Byte access is supported by upper
and lower byte controls.
The PDM41532 operates from a single 5.0V power
supply and all inputs and outputs are fully TTL-
compatible. The PDM41532 comes in two versions,
the standard power version PDM41532SA and a low
power version PDM41532LA. The two versions are
functionally the same and only differ in their power
consumption.
The PDM41532 is available in a 44-pin 400 mil plas-
tic SOJ and a 44-pin plastic TSOP (II) package
suitable for high-density surface assembly and is
suitable for use in high-speed applications such as
cache memory and high-speed storage.
1
2
3
4
5
6
7
n
High-speed access times
- Com’l: 10, 12, 15 and 20 ns
- Ind: 12, 15 and 20 ns
Low power operation (typical)
- PDM41532SA
Active: 350 mW
Standby: 50 mW
- PDM41532LA
Active: 300 mW
Standby: 25mW
High-density 64K x 16 architecture
Single +5V (±10%) power supply
Fully static operation
TTL-compatible inputs and outputs
Output buffer controls: OE
Data byte controls: LB, UB
Packages:
Plastic SOJ (400 mil) - SO
Plastic TSOP (II) - T
n
n
n
n
n
n
n
Functional Block Diagram
Row Address
Buffer
Row Decoder
Vcc
Vss
A8-A0
Memory
Cell
Array
256 x 128 x 32
8
9
10
11
I/O15-I/O0
Data
Input/
Output
Buffer
Sense Amp
Column
Decoder
WE
OE
UB
LB
CE
Control
Logic
Clock
Generator
Column
Address
Buffer
12
1
A15-A9
Rev. 1.3 - 4/10/98
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