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UT54ACS10-UCA

Description
NAND Gate, AC Series, 3-Func, 3-Input, CMOS, CDFP14, BOTTOM-BRAZED, CERAMIC, DFP-14
Categorylogic    logic   
File Size35KB,4 Pages
ManufacturerCobham PLC
Download Datasheet Parametric View All

UT54ACS10-UCA Overview

NAND Gate, AC Series, 3-Func, 3-Input, CMOS, CDFP14, BOTTOM-BRAZED, CERAMIC, DFP-14

UT54ACS10-UCA Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerCobham PLC
package instructionDFP, FL14,.3
Reach Compliance Codeunknow
seriesAC
JESD-30 codeR-CDFP-F14
JESD-609 codee0
Logic integrated circuit typeNAND GATE
MaximumI(ol)0.0001 A
Number of functions3
Number of entries3
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDFP
Encapsulate equivalent codeFL14,.3
Package shapeRECTANGULAR
Package formFLATPACK
power supply5 V
Prop。Delay @ Nom-Su16 ns
propagation delay (tpd)16 ns
Certification statusNot Qualified
Schmitt triggerNO
Maximum seat height2.921 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formFLAT
Terminal pitch1.27 mm
Terminal locationDUAL
width6.2865 mm
UT54ACS10/UT54ACTS10
Radiation-Hardened
Triple 3-Input NAND Gates
FEATURES
PINOUTS
14-Pin DIP
Top View
A1
B1
A2
B2
C2
Y2
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
C1
Y1
C3
B3
A3
Y3
radiation-hardened CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 14-pin DIP
- 14-lead flatpack
DESCRIPTION
The UT54ACS10 and the UT54ACTS10 are triple three-input
NAND gates. The circuits perform the Boolean functions
Y = A B C or Y = A + B + C in positive logic.
The devices are characterized over full military temperature
range of -55 C to +125 C.
FUNCTION TABLE
INPUTS
A
H
L
X
X
B
H
X
L
X
C
H
X
X
L
OUTPUT
Y
L
H
H
H
A1
B1
C1
A2
B2
C2
A3
B3
C3
(6)
Y2
14-Lead Flatpack
Top View
A1
B1
A2
B2
C2
Y2
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
C1
Y1
C3
B3
A3
Y3
LOGIC DIAGRAM
Y1
LOGIC SYMBOL
A1
B1
C1
A2
B2
C2
A3
B3
C3
(1)
(2)
(13)
(3)
(4)
(5)
(9)
(10)
(11)
(8)
Y3
(12)
Y1
Y2
Y3
Note:.
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and
IEC Publication 617-12.
17
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