Ordering number: EN 5228A
Thick Film Hybrid IC
STK672-050
Microstep Operation-Supported
4-Phase Stepping Motor Driver (I
O
= 3.0A)
Overview
The STK672-050 is a unipolar constant-current chopper-
type externally-excited 4-phase stepping motor driver
hybrid IC which uses MOSFET power devices. It has a
microstep operation-supported 4-phase distributed con-
troller built-in to realize a high torque, low vibration, low
noise stepping motor driver using a simple control circuit.
Package Dimensions
unit: mm
4164
[STK672-050]
Applications
• Printer, copier, and X-Y plotter stepping motor drivers
Features
• Microstep sine-wave driver operation using only an
external clock input (0.2
Ω
current detection resistor
built-in)
• Microstep drive using only an external reference voltage
setting resistor
• 2, 1-2, W1-2, 2W1-2, 4W1-2 phase excitation selectable
using external pins
• Selectable vector locus (perfect circle mode, inside 1
mode, outside 2 modes) to match motor characteristics
in microstep drive state
• Phase hold function during excitation switching
• Schmitt trigger inputs with built-in pull-up resistor
(20k
Ω
)
• Monitor output pin enabling real-time confirmation of
IC excitation
• The CLK and RETURN inputs provide an internal
noise elimination circuit as well as CMOS Schmitt cir-
cuit to prevent malfunction due to impulse noise.
• 4-phase distribution switch timing selected externally to
either CLK rising-edge only detection mode or both ris-
ing-edge and falling-edge detection mode
• ENABLE pin for excitation current cutoff, thereby
reducing system current drain when driver is stopped
Series Organization
The following devices form a series with differing output
capacity.
Type No.
STK672-040
STK672-050
Output current (A)
1.5
3.0
SANYO Electric Co., Ltd. Semiconductor Business Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
N2997HA(ID) / 11896HA(ID) No. 5228—1/11
STK672-050
Specifications
Maximum Ratings
at Ta = 25
°
C
Parameter
Maximum supply voltage 1
Maximum supply voltage 2
Input voltage
Phase output current
Repetitive avalanche handling capability
Maximum output dissipation
Operating substrate temperature
Junction temperature
Storage temperature
Symbol
V
CC
1 max
V
CC
2 max
V
IN
max
I
OH
max
Ear max
Pd max
Tc max
Tj max
Tstg
θ
c-a = 0
No signal
No signal
Logic input block
One 0.5s pulse, V
CC
1 applied,
Load/phase: R = 5
Ω
, L = 10mH
Conditions
Ratings
52
−
0.3 to +7.0
−
0.3 to +7.0
4.0
38
25
105
150
−
40 to +125
Unit
V
V
V
A
mJ
W
°
C
°
C
°
C
Allowable Operating Ranges
at Ta = 25
°
C
Parameter
Supply voltage 1
Supply voltage 2
Input voltage
Phase driver withstand voltage
Phase current
Symbol
V
CC
1
V
CC
2
V
IH
V
DSS
I
OH
max
Tr1, 2, 3, 4 (A, A, B, B outputs)
50% duty
With signal
With signal
Conditions
Ratings
10 to 45
5.0
±
5%
0 to V
CC
2
100 (min)
3.0 (max)
Unit
V
V
V
V
A
Electrical Characteristics
at Tc = 25
°
C, V
CC
1 = 24V, V
CC
2 = 5V
Parameter
Control supply current
Output saturation voltage
Average output current
FET diode forward voltage
[Control inputs]
Input voltage
V
IH
V
IL
Input current
[Vref input]
Input voltage
Input current
[Control outputs]
Output voltage
PWM frequency
[Current division ratio (A/B)]
2W1-2, W1-2, 1-2
2W1-2, W1-2
2W1-2
2W1-2, W1-2, 1-2
Vref
Vref
Vref
Vref
θ
= 1/8
θ
= 2/8
θ
= 3/8
θ
= 4/8
100
92
83
71
%
%
%
%
No. 5228—2/11
V
OH
V
OL
fc
I =
−
3mA (MoI, Mo1, Mo2 pins)
I = +3mA (MoI, Mo1, Mo2 pins)
2.4
–
37
–
–
47
–
0.4
57
V
V
kHz
V
I
I
I
Pin 8
Pin 8
0
–
–
1
2.5
–
V
µ
A
I
IH
I
IL
Excluding Vref pin
Excluding Vref pin
Excluding Vref pin
Excluding Vref pin
4.0
–
0
125
–
–
1
250
–
1.0
10
510
V
V
µ
A
µ
A
Symbol
I
CC
Vsat
Io ave
Vdf
Conditions
Pin 7 input, ENABLE = low
R
L
= 7.5
Ω
(I = 3A)
Vref = 0.6V,
Load/phase: R = 3.5
Ω
, L = 3.8mH
If = 1.0A
min
–
–
0.45
–
typ
4.5
1.4
0.50
1.2
max
15
2.6
0.55
1.8
Unit
mA
V
A
V
STK672-050
2W1-2
2W1-2, W1-2
2W1-2
2
Vref
Vref
Vref
Vref
θ
= 5/8
θ
= 6/8
θ
= 7/8
55
40
20
100
%
%
%
%
Note: All tests are made using a constant-voltage supply.
The current division ratio shows the design value.
Equivalent Block Diagram
Sample Application Circuit
2W1-2 phase excitation (microstep operation)
No. 5228—3/11
STK672-050
where Rs is the built-in current detection resistance (0.2
Ω
±
3%).
The motor current ranges from the current due to the fre-
quency duty set by the oscillator (0.05 to 0.1A) to the
allowable operating range maximum of I
OH
= 3.0A.
Motor Current Calculation
The motor current I
OH
is determined by the reference volt-
age on pin 8 (Vref). The relationship between I
OH
and
Vref is given by the following equation.
-
I
OH
= --
×
Vref
⁄
Rs
Motor current waveform
Function Tables
M1
0
0
1
1
0
0
1
1
M2
0
1
0
1
0
1
0
1
M3
0
0
0
0
1
1
1
1
CWB
0
1
Excitation
Phase 1-2
Phase 2W1-2
Rising and falling edge
Phase W1-2
Phase 4W1-2
Phase 2
Phase W1-2
Rising edge only
Phase 1-2
Phase 2W1-2
Direction
Forward
Reverse
Mo1
0
0
1
1
Mo2
0
1
0
1
Output
A
B
A
B
Phase switching CLK edge timing
Input
ENABLE
RESET
Active level
Low
Low
No. 5228—4/11
STK672-050
Design material
1. Explanation of input pins
Pin No.
14
15
17
18
9, 10, 11
12, 13
16
8
CLK
CWB
RETURN
ENABLE
M1, M2, M3
M4, M5
RESET
Vref
Name
Function
Phase switching clock
Setting of rotation direction (CW/CCW)
Phase origin forced return
Output cut-off
Setting of excitation mode
Setting of vector locus
System reset
Setting of current value
Pin format
CMOS Schmitt configuration with pull-up resistor
CMOS Schmitt configuration with pull-up resistor
CMOS Schmitt configuration with pull-up resistor
CMOS Schmitt configuration with pull-up resistor
CMOS Schmitt configuration with pull-up resistor
CMOS Schmitt configuration with pull-up resistor
CMOS Schmitt configuration with pull-up resistor
CMOS Schmitt configuration with pull-up resistor
2. Functions and timing of input signals
2-1. CLK (Phase switching clock)
1. Input frequency range
2. Minimum pulse width
3. Duty
4. Pin format
6. Functions
a. When the signal M3 is set to 1 or it is opened.
The excitation phase moves at each step at the rising edge of the clock.
b. When the signal M3 is set to 0.
The excitation phase moves at each step at the rising and falling edges of the clock.
s
DC to 50 kHz
s
10
µ
s
s
40 to 60%
s
CMOS Schmitt configuration containing pull-up resistor (20 k
Ω
typical value)
5. Noise eliminating circuit with multiple stages is contained.
2-2. CWB (Setting of rotation direction)
1. Pin format
2. Function
a. When the signal CWB is set to 1.
It rotates clockwise.
b. When the signal CWB is set to 0.
It rotates counterclockwise.
3. Note
s
When the signal M3 is set to 0, the CWB input signal must not be changed
at the rising edge and falling edge of the clock input for the period of 5
µ
s.
s
CMOS Schmitt configuration containing pull-up resistor
(20k
Ω
, typical value)
No. 5228—5/11
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