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EQRD12L2L-132.813MTR

Description
CRYSTAL OSCILLATOR, CLOCK, LVPECL OUTPUT
CategoryPassive components    oscillator   
File Size1MB,12 Pages
ManufacturerECLIPTEK
Websitehttp://www.ecliptek.com
Environmental Compliance
Download Datasheet Parametric View All

EQRD12L2L-132.813MTR Overview

CRYSTAL OSCILLATOR, CLOCK, LVPECL OUTPUT

EQRD12L2L-132.813MTR Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerECLIPTEK
Reach Compliance Codecompli
Other featuresSTANDBY; ENABLE/DISABLE FUNCTION; COMPLEMENTARY OUTPUT; TR, 14 INCH
maximum descent time0.5 ns
Frequency Adjustment - MechanicalNO
frequency stability25%
JESD-609 codee4
Installation featuresSURFACE MOUNT
Nominal operating frequency132.813 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeLVPECL
Output load50 OHM
physical size7.0mm x 5.0mm x 1.8mm
longest rise time0.5 ns
Maximum supply voltage2.625 V
Minimum supply voltage2.375 V
Nominal supply voltage2.5 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
Ecliptek | EQRD12 Series Oscillator
http://www.ecliptek.com/oscillators/EQRD12/
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| 714-433-1200 |
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EQRD12 Series Oscillator
Quartz Crystal Clock Oscillators XO (SPXO) LVPECL (PECL) 2.5Vdc 6 Pad 5.0mm x 7.0mm Ceramic Surface Mount (SMD)
2011/65 +
2015/863
168 SVHC
Revision C 06/11/2014
Electrical Specifications
Nominal Frequency
10.000MHz to 200.000MHz
Some frequencies within this range may not be available.
Frequency Tolerance/Stability
Inclusive of all conditions: Calibration Tolerance (at 25°C), Frequency
Stability over the Operating Temperature Range, Supply Voltage
Change, Output Load Change, First Year Aging at 25°C, Shock, and
Vibration
±100ppm Maximum
±50ppm Maximum
±25ppm Maximum
±20ppm Maximum
0°C to +70°C
-20°C to +70°C
-40°C to +85°C
±3ppm Maximum First Year
2.5V
DC
±5%
50mA Maximum
V
DD
-1.025V
DC
Minimum, 1.55V
DC
Typical, V
DD
-0.88V
DC
Maximum
V
DD
-1.81V
DC
Minimum, 0.80V
DC
Typical, V
DD
-1.62V
DC
Maximum
Measured at 50% of waveform
50 ±10(%)
50 ±5(%)
Measured at 20% to 80% of Waveform
400pSec Maximum
50 Ohms into V
DD
-2.0V
DC
LVPECL
Click to Open Phase Noise Table
Standby (on Pad 1)
Standby (on Pad 2)
70% of V
DD
Minimum or No Connect to Enable Output and
Complementary Output
30% of V
DD
Maximum to Disable Output and Complementary Output
(High Impedance)
10mSec Maximum
200nSec Maximum
Operating Temperature Range
Aging at 25°C
Supply Voltage
Input Current
Output Voltage Logic High (V
OH
)
Output Voltage Logic Low (V
OL
)
Duty Cycle
Rise Time/Fall Time
Load Drive Capability
Output Logic Type
Phase Noise
Output Control Function
Output Control Input Voltage Logic High
(Vih)
Output Control Input Voltage Logic Low
(Vil)
Standby Output Enable Time
Standby Output Disable Time
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28-Jan-2016 2:18 PM

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