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UT54ACS00-PQAH

Description
NAND Gate, CMOS, CDIP14
Categorylogic    logic   
File Size225KB,9 Pages
ManufacturerAeroflex
Websitehttp://www.aeroflex.com/
Download Datasheet Parametric View All

UT54ACS00-PQAH Overview

NAND Gate, CMOS, CDIP14

UT54ACS00-PQAH Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerAeroflex
package instructionDIP, DIP14,.3
Reach Compliance Codeunknow
JESD-30 codeR-XDIP-T14
JESD-609 codee0
Logic integrated circuit typeNAND GATE
MaximumI(ol)0.0001 A
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialCERAMIC
encapsulated codeDIP
Encapsulate equivalent codeDIP14,.3
Package shapeRECTANGULAR
Package formIN-LINE
power supply5 V
Prop。Delay @ Nom-Su14 ns
Certification statusNot Qualified
Schmitt triggerNO
Filter level38535Q/M;38534H;883B
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
total dose1M Rad(Si) V
Standard Products
UT54ACS00/UT54ACTS00
Quadruple 2-Input NAND Gates
Datasheet
November, 2010
www.aeroflex.com/logic
FEATURES
1.2μ
CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 14-pin DIP
- 14-lead flatpack
UT54ACS00 - SMD 5962-96512
UT54ACTS00 - SMD 5962-96513
DESCRIPTION
The UT54ACS00 and the UT54ACTS00 are quadruple, two-
input NAND gates. The circuits perform the Boolean functions
Y = A⋅B or Y = A + B in positive logic.
The devices are characterized over full military temperature
range of -55°C to +125°C.
FUNCTION TABLE
INPUTS
A
H
L
X
B
H
X
L
OUTPUT
Y
L
H
H
PINOUTS
14-Pin DIP
Top View
A1
B1
Y1
A2
B2
Y2
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
B4
A4
Y4
B3
A3
Y3
14-Lead Flatpack
Top View
A1
B1
Y1
A2
B2
Y2
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
B4
A4
Y4
B3
A3
Y3
LOGIC DIAGRAM
LOGIC SYMBOL
A1
B1
A1
B1
A2
B2
A3
B3
A4
B4
(1)
(2)
(4)
(5)
(9)
(10)
(12)
(13)
(11)
(6)
(8)
Y2
Y3
Y4
&
(3)
Y1
A2
B2
A3
B3
A4
B4
Y4
Y3
Y1
Y2
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC
Publication 617-12.
1

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