The UT54LVDM228 provides three modes of operation. In
the 1:2 splitter mode, the two outputs are copies of the same
single input. This is useful for distribution / fan-out
applications. In the repeater mode, the device operates as a
9channel LVDS buffer. Repeating the signal restores the
LVDS amplitude, allowing it to drive another media segment.
This allows for isolation of segments or long distance
applications or buffers standard LVDS to 10mA multi-op
drivers.The switch mode provides a crosspoint function. This
can be used in a system when primary and redundant paths
are supported in a fault tolerant application.
The intended application of these devices and signaling
technique is for both point-to-point baseband (single
termination) and multipoint (double termination) data
transmissions over controlled impedance media. The
transmission media may be printed-circuit board traces,
backplanes, or cables. (Note: The ultimate rate and distance
of data transfer is dependent upon the attenuation
characteristics of th
e media, the noise coupling to the
environment, and other application specific
characteristics.
The outer layers of the PCB may be flooded with additional
ground plane. These planes will improve shielding and
isolation, as well as increase the intrinsic capacitance of the
power supply plane system. Naturally, to be effective, these
planes must be tied to the ground supply plane at frequent
intervals with vias. Frequent via placement also improves
signal integrity in signal transmission lines by providing short
paths for image currents which reduces signal distortion. The
planes should be pulled back from all transmission lines and
component mounting pads a distance equal to the width of
the widest transmission line from the internal power or
ground plane(s) whichever is greater. Doing so minimizes
effects on transmission line impedances and reduces
unwanted parasitic capacitances at component mounting
pads.
Compatibility with LVDS standard:
In backplane multidrop configurations, with closely spaced
loads, the effective differential impedance of the line is
reduced. If the mainline has been designed for 50Ω
differential impedance, the loading effects may reduce this to
the 35Ω range depending upon spacing and capacitance load.
Terminating the line with a 35Ω load is a better match than
with 50Ω and reflections are reduced.
Input Fail-Safe:
The UT54LVDM228 also supports OPEN, shorted and
terminated input fail-safe. Receiver output will be HIGH for
all fail-safe conditions.
PCB layout and Power System Bypass:
Circuit board layout and stack-up for the UT54LVDM228
should be designed to provide noise-free power to the device.
Good layout practice also will separate high frequency or high
level inputs and outputs to minimize unwanted stray noise
pickup, feedback and interference. Power system
performance may be greatly improved by using thin
dielectrics (4 to 10 mils) for power/ground sandwiches. This
increases the intrinsic capacitance of the PCB power system
which improves power supply filtering, especially at high
frequencies, and makes the value and placement of external
bypass capacitors less critical. External bypass capacitors
should include both RF ceramic and tantalum electrolytic
types. RF capacitors may use values in the range 0.01μF to
0.1μ F. Tantalum capacitors may be in the range of 2.2μF to
10μF. Voltage rating for tantalum capacitors should be at least
5X the power supply voltage being used. It is recommended
practice to use two vias at each power pin of the
UT54LVDM228, as well as all RF bypass capacitor
terminals. Dual vias reduce the interconnect inductance and
extends the effective frequency range of the bypass
components.
4
OPERATIONAL ENVIRONMENT
PARAMETER
Total Ionizing Dose (TID)
Single Event Latchup (SEL)
Neutron Fluence
1
Notes:
1. Guarnteed but not tested.
LIMIT
1.0E6
>100
1.0E13
UNITS
rad(Si)
MeV-cm
2
/mg
n/cm
2
ABSOLUTE MAXIMUM RATINGS
1
(Referenced to V
SS
)
SYMBOL
V
DD
V
I/O4
T
STG
P
D
T
J
Θ
JC
I
I
PARAMETER
DC supply voltage
Voltage on any pin
Storage temperature
Maximum power dissipation
Maximum junction temperature
2
Thermal resistance, junction-to-case
3
DC input current
LIMITS
-0.3 to 4.0V
-0.3 to (V
DD
+ 0.3V)
-65 to +150°C
800mW
+150°C
22°C/W
±
10mA
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Maximum junction temperature may be increased to +175°C during burn-in and life test.
3. Test per MIL-STD-883, Method 1012.
4. For Cold Spare mode (V
DD
=V
SS
), V
I/O
may be -0.3V to the maximum recommended operating V
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