address inputs, A(18:0); and eight bidirectional data lines,
DQ(7:0). E1 and E2 device enables control device selection,
active, and standby modes. Asserting E1 and E2 enables the
device, causes I
DD
to rise to its active value, and decodes the 19
address inputs to select one of 524,288 words in the memory.
W controls read and write operations. During a read cycle, G
must be asserted to enable the outputs.
Table 1. Device Operation Truth Table
G
X
W
X
X
0
1
1
E2
X
0
1
1
1
E1
1
X
0
0
0
I/O Mode
3-state
3-state
Data in
3-state
Data out
Mode
Standby
Standby
Write
Read
2
Read
Figure 2. 10ns SRAM Pinout (36)
X
X
1
A(18:0)
DQ(7:0)
E1
E2
Address
Data Input/Output
Enable
Enable
W
G
V
DD1
V
DD2
V
SS
WriteEnable
Output Enable
Power (1.8V)
Power (2.5V)
Ground
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
D
EV
IN
EL
O
2
PM
READ CYCLE
A combination of W and E2 greater than V
IH
(min) and E1 less
than V
IL
(max) defines a read cycle. Read access time is
measured from the latter of device enable, output enable, or valid
address to valid data output.
SRAM Read Cycle 1, the Address Access in Figure 3a, is
initiated by a change in address inputs while the chip is enabled
with G asserted and W deasserted. Valid data appears on data
outputs DQ(7:0) after the specified t
AVQV
is satisfied. Outputs
remain active throughout the entire cycle. As long as device
enable and output enable are active, the address inputs may
change at a rate equal to the minimum read cycle time (t
AVAV
).
SRAM Read Cycle 2, the Chip Enable-controlled Access in
Figure 3b, is initiated by E1 and E2 going active while G remains
asserted, W remains deasserted, and the addresses remain stable
for the entire cycle. After the specified t
ETQV
is satisfied, the
eight-bit word addressed by A(18:0) is accessed and appears at
the data outputs DQ(7:0).
SRAM Read Cycle 3, the Output Enable-controlled Access in
Figure 3c, is initiated by G going active while E1 and E2 are
asserted, W is deasserted, and the addresses are stable. Read
access time is t
GLQV
unless t
AVQV
or t
ETQV
have not been
satisfied.
EN
PIN NAMES
0
T
WRITE CYCLE
A combination of W and E1 less than V
IL
(max) and E2
greater than V
IH
(min) defines a write cycle. The state of G is
a “don’t care” for a write cycle. The outputs are placed in the
high-impedance state when eitherG is greater than V
IH
(min),
or when W is less than V
IL
(max).
Write Cycle 1, the Write Enable-controlled Access in Figure
4a, is defined by a write terminated by W going high, with
E1 and E2 still active. The write pulse width is defined by
t
WLWH
when the write is initiated by W, and by t
ETWH
when
the write is initiated by E1 or E2. Unless the outputs have
been previously placed in the high-impedance state byG, the
user must wait t
WLQZ
before applying data to the nine
bidirectional pins DQ(7:0) to avoid bus contention.
Write Cycle 2, the Chip Enable-controlled Access in Figure
4b, is defined by a write terminated by the latter of E1 or E2
going inactive. The write pulse width is defined by t
WLEF
when the write is initiated byW, and by t
ETEF
when the write
is initiated by either E1or E2 going active. For the W initiated
write, unless the outputs have been previously placed in the
high-impedance state by G, the user must wait t
WLQZ
before
applying data to the eight bidirectional pins DQ(7:0) to avoid
bus contention.
RADIATION HARDNESS
The UT8R512K8 SRAM incorporates special design and
layout features which allows operation in a limited radiation
environment.
Table 2. Radiation Hardness
Design Specifications
1
Total Dose
Heavy Ion
Error Rate
2
100K
1.0E-10
rad(Si)
Errors/Bit-Day
Notes:
1. The SRAM is immune to latchup.
2. 10% worst case particle environment, Geosynchronous orbit, 0.025 mils
of Aluminum.
Supply Sequencing
IN
D
EV
EL
O
3
PM
EN
T
No supply voltage sequencing is required between V
DD1
and
V
DD2
.
ABSOLUTE MAXIMUM RATINGS
1
(Referenced to V
SS
)
SYMBOL
V
DD1
V
DD2
V
I/O
T
STG
P
D
T
J
Θ
JC
I
I
PARAMETER
DC supply voltage
DC supply voltage
Voltage on any pin
Storage temperature
Maximum power dissipation
Maximum junction temperature
2
Thermal resistance, junction-to-case
3
DC input current
LIMITS
-0.3 to 2.0V
-0.3 to 3.8V
-0.3 to 3.8V
-65 to +150°C
1.2W
+150°C
5°C/W
±
5 mA
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD1
V
DD2
T
C
V
IN
PARAMETER
Positive supply voltage
Positive supply voltage
Case temperature range
DC input voltage
EL
O
4
IN
D
EV
PM
EN
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.
3. Test per MIL-STD-883, Method 1012.
-55 to +125°C
0V to V
DD2
T
LIMITS
1.7 to 1.9V
2.25 to 3.6V
DC ELECTRICAL CHARACTERISTICS (Pre and Post-Radiation)*
(-55°C to +125°C)
SYMBOL
V
IH
V
IL
V
OL1
V
OH1
C
IN 1
C
IO 1
I
IN
I
OZ
PARAMETER
High-level input voltage
Low-level input voltage
Low-level output voltage
High-level output voltage
Input capacitance
Bidirectional I/O capacitance
Input leakage current
Three-state output leakage
current
Short-circuit output current
I
OL
= 8mA,V
DD2
=V
DD2
(min)
I
OH
= -4mA,V
DD2
=V
DD2
(min)
ƒ
= 1MHz @ 0V
ƒ
= 1MHz @ 0V
V
IN
= V
DD2
and V
SS
V
O
= V
DD2
and V
SS,
V
DD2
= V
DD2
(max)
G = V
DD2
(max)
V
DD2
= V
DD2
(max), V
O
= V
DD2
V
DD2
= V
DD2
(max), V
O
= V
SS
I
DD1
(OP
1
)
Supply current operating
@ 1MHz
Inputs : V
IL
= V
SS
+ 0.2V
-80
+80
mA
-2
-2
.8*V
DD2
7
7
2
2
CONDITION
MIN
.7*V
DD2
.3*V
DD2
.2*V
DD2
MAX
UNIT
V
V
V
V
pF
pF
µA
µA
PM
EN
T
1
mA
30
mA
5
mA
115
mA
1
mA
5
mA
I
OS 2, 3
V
IH
= V
DD2
+ 0.2V, I
OUT
= 0
V
DD1
= V
DD1
(max), V
DD2
= V
DD2
(max)
I
DD1
(OP
2
)
Supply current operating
@100MHz
Inputs : V
IL
= V
SS
+ 0.2V,
V
IH
= V
DD2
+ 0.2V, I
OUT
= 0
V
DD1
= V
DD1
(max), V
DD2
= V
DD2
(max)
I
DD2
(OP
1
)
Supply current operating
@ 1MHz
I
DD2
(OP
2
)
D
I
DD
(SB)
4
Total Supply current standby
A(18:0) static (0Hz)
I
DD
(SB)
4
Total Supply current standby
A(18:0) @ 10MHz
IN
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1.0E5 rad(Si).
1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.
2. Supplied as a design limit but not guaranteed or tested.
3. Not more than one output may be shorted at a time for maximum duration of one second.
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FPGA/CPLD
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