HEF4094B
8-stage shift-and-store register
Rev. 11 — 29 August 2013
Product data sheet
1. General description
The HEF4094B is an 8-stage serial shift register. It has a storage latch associated with
each stage for strobing data from the serial input to parallel buffered 3-state outputs
QP0 to QP7. The parallel outputs may be connected directly to common bus lines. Data is
shifted on positive-going clock transitions. The data in each shift register stage is
transferred to the storage register when the strobe (STR) input is HIGH. Data in the
storage register appears at the outputs whenever the output enable (OE) signal is HIGH.
Two serial outputs (QS1 and QS2) are available for cascading a number of HEF4094B
devices. Serial data is available at QS1 on positive-going clock edges to allow high-speed
operation in cascaded systems with a fast clock rise time. The same serial data is
available at QS2 on the next negative going clock edge. This is used for cascading
HEF4094B devices when the clock has a slow rise time.
It operates over a recommended V
DD
power supply range of 3 V to 15 V referenced to V
SS
(usually ground). Unused inputs must be connected to V
DD
, V
SS
, or another input.
2. Features and benefits
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from
40 C
to +85
C
and
40 C
to +125
C
Complies with JEDEC standard JESD 13-B
3. Ordering information
Table 1.
Ordering information
All types operate from
40
C to +125
C.
Type number
HEF4094BP
HEF4094BT
HEF4094BTS
HEF4094BTT
Package
Name
DIP16
SO16
SSOP16
TSSOP16
Description
plastic dual in-line package; 16 leads (300 mil)
plastic small outline package; 16 leads; body width 3.9 mm
plastic shrink small outline package; 16 leads; body width 5.3 mm
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
Version
SOT38-4
SOT109-1
SOT338-1
SOT403-1
NXP Semiconductors
HEF4094B
8-stage shift-and-store register
4. Functional diagram
3
CP
2
3
D
CP
8-STAGE SHIFT
REGISTER
QS2
QS1
STR
8-BIT STORAGE
REGISTER
2
OE
D
QP3
QP4
3-STATE OUTPUTS
QP5
QP0 QP1 QP2 QP3 QP4 QP5 QP6 QP7
4
5
6
7
14
13
12
11
001aaf119
1
STR
QS1
9
10
4
5
6
7
14
13
12
11
10
9
QS2
QP0
QP1
QP2
1
15
QP6
QP7
OE
15
001aaf111
Fig 1.
Functional diagram
Fig 2.
Logic symbol
STAGE 0
D
D
CP
FF 0
CP
CP
Q
D
STAGES 1 TO 6
Q
STAGE 7
D
CP
FF 7
D
LE
LATCH
Q
QS2
Q
QS1
D
LE
Q
D
LE
Q
LATCH 0
STR
LATCH 7
OE
QP0
QP1
QP2
QP3
QP4
QP5
QP6
QP7
001aag799
Fig 3.
Logic diagram
HEF4094B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 11 — 29 August 2013
2 of 20
NXP Semiconductors
HEF4094B
8-stage shift-and-store register
5. Pinning information
5.1 Pinning
HEF4094B
STR
D
CP
QP0
QP1
QP2
QP3
V
SS
1
2
3
4
5
6
7
8
001aae662
16 V
DD
15 OE
14 QP4
13 QP5
12 QP6
11 QP7
10 QS2
9
QS1
Fig 4.
Pin configuration SOT38-4 and SOT109-1
Fig 5.
Pin configuration SOT338-1 and SOT403-1
5.2 Pin description
Table 2.
Symbol
STR
D
CP
QP0 to QP7
V
SS
QS1
QS2
OE
V
DD
Pin description
Pin
1
2
3
4, 5, 6, 7, 14, 13, 12, 11
8
9
10
15
16
Description
strobe input
data input
clock input
parallel output
ground supply voltage
serial output
serial output
output enable input
supply voltage
HEF4094B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 11 — 29 August 2013
3 of 20
NXP Semiconductors
HEF4094B
8-stage shift-and-store register
6. Functional description
Table 3.
Inputs
CP
[1]
Function table
[1]
Parallel outputs
OE
L
L
H
H
H
H
STR
X
X
L
H
H
H
D
X
X
X
L
H
H
QP0
Z
Z
NC
L
H
NC
QPn
Z
Z
NC
QPn
1
QPn
1
NC
Serial outputs
QS1
Q6S
NC
Q6S
Q6S
Q6S
NC
QS2
NC
Q7S
NC
NC
NC
Q7S
At the positive clock edge, the information in the 7th register stage is transferred to the 8th register stage and the QSn outputs.
H = HIGH voltage level; L = LOW voltage level; X = don’t care;
= positive-going transition;
= negative-going transition;
Z = HIGH-impedance OFF-state; NC = no change;
Q6S = the data in register stage 6 before the LOW to HIGH clock transition;
Q7S = the data in register stage 7 before the HIGH to LOW clock transition.
CLOCK INPUT
DATA INPUT
STROBE INPUT
OUTPUT ENABLE INPUT
INTERNAL Q0S (FF 0)
OUTPUT QP0
INTERNAL Q6S (FF 6)
OUTPUT QP6
SERIAL OUTPUT QS1
SERIAL OUTPUT QS2
001aaf117
Z-state
Z-state
Fig 6.
Timing diagram
HEF4094B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 11 — 29 August 2013
4 of 20
NXP Semiconductors
HEF4094B
8-stage shift-and-store register
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to V
SS
= 0 V (ground).
Symbol
V
DD
I
IK
V
I
I
OK
I
I/O
I
DD
T
stg
T
amb
P
tot
P
[1]
[2]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
input/output current
supply current
storage temperature
ambient temperature
total power dissipation
power dissipation
Conditions
V
I
<
0.5
V or V
I
> V
DD
+ 0.5 V
V
O
<
0.5
V or V
O
> V
DD
+ 0.5 V
Min
0.5
-
0.5
-
-
-
65
40
Max
+18
10
V
DD
+ 0.5
10
10
50
+150
+125
750
500
100
Unit
V
mA
V
mA
mA
mA
C
C
mW
mW
mW
DIP16
SO16, SSOP16 and TSSOP16
per output
[1]
[2]
-
-
-
For DIP16 packages: above T
amb
= 70
C,
P
tot
derates linearly with 12 mW/K.
For SO16 package: P
tot
derates linearly with 8 mW/K above 70
C.
For (T)SSOP16 package: P
tot
derates linearly with 5.5 mW/K above 60
C.
8. Recommended operating conditions
Table 5.
Symbol
V
DD
V
I
T
amb
t/V
Recommended operating conditions
Parameter
supply voltage
input voltage
ambient temperature
input transition rise and fall rate
in free air
V
DD
= 5 V
V
DD
= 10 V
V
DD
= 15 V
Conditions
Min
3
0
40
-
-
-
Typ
-
-
-
-
-
-
Max
15
V
DD
+125
3.75
0.5
0.08
Unit
V
V
C
s/V
s/V
s/V
HEF4094B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 11 — 29 August 2013
5 of 20
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