HFBR-5961LZ/ALZ/GZ/AGZ
Multimode Small Form Factor (SFF) Transceivers for ATM, FDDI,
Fast Ethernet and SONET OC-3/SDH STM-1 with LC connector
Data Sheet
Description
The HFBR-5961xxZ transceiver from Avago provides the
system designer with a product to implement a range of
solutions for multimode fiber Fast Ethernet and SONET
OC-3 (SDH STM-1) physical layers for ATM and other
services.
This transceiver is supplied in the industry standard 2 x
5 DIP style with an LC fiber connector interface with an
external connector shield.
Features
•
Multisourced 2 x 5 package style
•
Operates with 62.5/125 µm and 50/125 µm multimode
fiber
•
Single +3.3 V power supply
•
Wave solder and aqueous wash process compatibil-
ity
•
Manufactured in an ISO 9001 certified facility
•
Full compliance with ATM Forum
•
UNI SONET OC-3 multimode fiber physical layer speci-
fication
•
Full compliance with the optical performance require-
ments of the FDDI PMD standard
•
Full compliance with the optical performance require-
ments of 100Base-FX version of IEEE802.3u
•
RoHS compliant
•
PECL Signal Detect Output
•
Temperature range:
HFBR-5961LZ
0 °C to +70 °C
HFBR-5961ALZ
-40 °C to +85 °C
HFBR-5961GZ
0 °C to +70°C (No EMI shield)
HFBR-5961AGZ
-40 °C to +85°C (No EMI shield)
Transmitter Section
The transmitter section of the HFBR-5961xxZ utilizes
a 1300 nm InGaAsP LED. This LED is packaged in the
optical subassembly portion of the transmitter section.
It is driven by a custom silicon IC which converts differ-
ential PECL logic signals, ECL referenced (shifted) to a
+3.3 V supply, into an analog LED drive current.
Receiver Section
The receiver section of the HFBR-5961xxZ utilizes an
InGaAs PIN photodiode coupled to a custom silicon
transimpedance preamplifier IC. It is packaged in the
optical subassembly portion of the receiver.
This PIN/preamplifier combination is coupled to a
custom quantizer IC which provides the final pulse
shaping for the logic output and the Signal Detect
function. The Data output is differential. The Signal
Detect output is single ended. Both Data and Signal
Detect outputs are PECL compatible, ECL referenced
(shifted) to a +3.3 V power supply. The receiver
outputs, Data Output and Data Out Bar, are squelched
at Signal Detect deassert. That is, when the light input
power decreases to a typical -38 dBm or less, the Signal
Detect deasserts, ie. the Signal Detect output goes to a
PECL low state. This forces the receiver outputs, Data
Out and Data Out Bar to go steady PECL levels high and
low respectively.
Applications
•
SONET/SDH equipment interconnect, OC-3/SDH
STM-1 rate
•
Fast Ethernet
•
Multimode fiber ATM backbone links
Package
The overall package concept for the Avago transceiver
consists of three basic elements; the two optical subas-
semblies, an electrical subassembly, and the housing as
illustrated in the block diagram in Figure 1.
The package outline drawing and pin out are shown in
Figures 2 and 5. The details of this package outline and
pin out are compliant with the multisource definition of
the 2 x 5 DIP. The low profile of the Avago transceiver
design complies with the maximum height allowed for
the LC connector over the entire length of the package.
The optical subassemblies utilize a high-volume
assembly process together with low-cost lens elements
which result in a cost effective building block.
The electrical subassembly consists of a high volume
multilayer printed circuit board on which the ICs and
various surface mounted passive circuit elements are
attached.
The receiver section includes an internal shield for the
electrical and optical subassemblies to ensure high
immunity to external EMI fields.
The outer housing including the LC ports is molded
of filled nonconductive plastic to provide mechani-
cal strength. The solder posts of the Avago design are
isolated from the internal circuit of the transceiver.
The transceiver is attached to a printed circuit board
with the ten signal pins and the two solder posts which
exit the bottom of the housing. The two solder posts
provide the primary mechanical strength to withstand
the loads imposed on the transceiver by mating with
the LC connector fiber cables.
RXSUPPLY
DATA OUT
DATA OUT
SIGNAL
DETECT
DATA IN
DATA IN
LED DRIVER IC
QUANTIZER IC
RXGROUND
TXGROUND
PIN PHOTODIODE
PRE-AMPLIFIER
SUBASSEMBLY
LC
RECEPTACLE
LED
OPTICAL
SUBASSEMBLY
TXSUPPLY
Figure 1. Block Diagram
2
RX
TX
Mounting
Studs/Solder
Posts
Pin 7 Transmitter Signal Ground V
EE
TX:
Directly connect this pin to the transmitter ground
plane.
Pin 8 NC:
No connection.
Top
View
Pin 9 Transmitter Data In TD+:
No internal terminations are provided. See recom-
mended circuit schematic.
10
9
8
7
6
o
o
o
o
o
TRANSMITTER DATA IN BAR
TRANSMITTER DATA IN
NC
TRANSMITTER SIGNAL GROUND
TRANSMITTER POWER SUPPLY
RECEIVER SIGNAL GROUND
RECEIVER POWER SUPPLY
SIGNAL DETECT
RECEIVER DATA OUT BAR
RECEIVER DATA OUT
o
o
o
o
o
1
2
3
4
5
Pin 10 Transmitter Data In Bar TD-:
No internal terminations are provided. See recom-
mended circuit schematic.
Mounting Studs/Solder Posts
The mounting studs are provided for transceiver me-
chanical attachment to the circuit board. It is rec-
ommended that the holes in the circuit board be
connected to chassis ground.
Figure 2. Pin Out Diagram
Pin Descriptions:
Pin 1 Receiver Signal Ground V
EE
RX:
Directly connect this pin to the receiver ground plane.
Application Information
The Applications Engineering group is available to assist
you with the technical understanding and design trade-
offs associated with these transceivers. You can contact
them through your Avago sales representative.
The following information is provided to answer some
of the most common questions about the use of these
parts.
Pin 2 Receiver Power Supply V
CC
RX:
Provide +3.3 V dc via the recommended receiver power
supply filter circuit. Locate the power supply filter
circuit as close as possible to the V
CC
RX pin.
Pin 3 Signal Detect SD:
Normal optical input levels to the receiver result in a
logic “1” output.
Low optical input levels to the receiver result in a logic
“0” output.
This Signal Detect output can be used to drive a PECL
input on an upstream circuit, such as Signal Detect
input of Loss of Signal-Bar.
Transceiver Optical Power Budget versus Link Length
Optical Power Budget (OPB) is the available optical
power for a fiber optic link to accommodate fiber cable
losses plus losses due to in-line connectors, splices,
optical switches, and to provide margin for link aging
and unplanned losses due to cable plant reconfigura-
tion or repair.
Avago LED technology has produced 1300 nm LED
devices with lower aging characteristics than normally
associated with these technologies in the industry.
The industry convention is 1.5 dB aging for 1300 nm
LEDs. The 1300 nm Avago LEDs are specified to expe-
rience less than 1 dB of aging over normal commercial
equipment mission life periods. Contact your Avago
sales representative for additional details.
Pin 4 Receiver Data Out Bar RD-:
No internal terminations are provided. See recom-
mended circuit schematic.
Pin 5 Receiver Data Out RD+:
No internal terminations are provided. See recom-
mended circuit schematic.
Pin 6 Transmitter Power Supply V
CC
TX:
Provide +3.3 V dc via the recommended transmitter
power supply filter circuit. Locate the power supply
filter circuit as close as possible to the V
CC
TX pin.
3
Recommended Handing Precautions
Avago recommends that normal status precautions be
taken in the handling and assembly of these transceiv-
ers to prevent damage which may be induced by elec-
trostatic discharge (ESD). The HFBR-5961xxZ series of
transceivers meet MIL-STD-883C Method 3015.4 Class 2
products.
Care should be used to avoid shorting the receiver data
or signal detect outputs directly to ground without
proper current limiting impedance.
Shipping Container
The transceiver is packaged in a shipping container
designed to protect it from mechanical and ESD
damage during shipment of storage.
Board Layout - Decoupling Circuit, Ground Planes and Termi-
nation Circuits
It is important to take care in the layout of your circuit
board to achieve optimum performance from these
transceivers. Figure 3 provides a good example of a
schematic for a power supply decoupling circuit that
works will with these parts, It is further recommend-
ed that a contiguous ground plane be provided in the
circuit board directly under the transceiver to provide
a low inductance ground for signal return current.
This recommendation is in keeping with good high
frequency board layout practices. Figures 3 and 4 show
two recommended termination schemes.
Solder and Wash Process Compatibility
The transceivers are delivered with protective process
plugs inserted into the LC receptacle.
This process plug protects the optical subassemblies
during wave solder and aqueous wash processing and
acts as a dust cover during shipping.
These transceivers are compatible with either industry
standard wave or hand solder processes.
PHY DEVICE
VCC(+3.3 V)
TERMINATE AT
TRANSCEIVER INPUTS
Z = 50
Ω
TD-
LVPECL
TD+
130
Ω
130
Ω
100
Ω
Z = 50
Ω
10
9
8
7
6
1 µH
C2
VCC(+3.3 V)
C3
10 µF
TD- o
TD+ o
N/C o
TX
RX
VEETX o
VCCTX o
VCC(+3.3 V)
o VEERX
o VCCRX
o RD+
o RD-
o SD
1 µH
C1
Z = 50
Ω
100
Ω
RD-
Z = 50
Ω
VCC(+3.3 V)
130
Ω
SD
82
Ω
LVTTL
RD+
LVPECL
1
2
3
4
5
130
Ω
130
Ω
Z = 50
Ω
Notes:
C1 = C2 = C3 = 10 nF or 100 nF
* Loading of R1 is optional.
TERMINATE AT
DEVICE INPUTS
Figure 3. Recommended Decoupling and Termination Circuits
4
Board Layout - Hole Pattern
The Avago transceiver complies with the circuit board
“Common Transceiver Footprint” hole pattern defined in
the original multisource announcement which defined
the 2 x 5 package style. This drawing is reproduced in
Figure 6 with the addition of ANSI Y14.5M compliant
dimensioning to be used as a guide in the mechani-
cal layout of your circuit board. Figure 6 illustrates the
recommended panel opening and the position of the
circuit board with respect to this panel.
Regulatory Compliance
These transceiver products are intended to enable
commercial system designers to develop equipment
that complies with the various international regula-
tions governing certification of Information Technology
Equipment. See the Regulatory Compliance Table for
details. Additional information is available from your
Avago sales representative.
TERMINATE AT
TRANSCEIVER INPUTS
VCC(+3.3 V)
PHY DEVICE
10 nF
130
Ω
130
Ω
Z = 50
Ω
TD-
VCC(+3.3 V)
Z = 50
Ω
LVPECL
TD+
10
9
8
7
6
82
Ω
82
Ω
VCC(+3.3 V)
TD- o
TD+ o
N/C o
VEETX o
VCCTX o
TX
RX
1 µH
C2
VCC(+3.3 V)
C3
10 µF
10 nF
130
Ω
130
Ω
RD+
VCC(+3.3 V)
o VEERX
o VCCRX
o RD+
o RD-
o SD
1 µH
C1
1
2
3
4
5
Z = 50
Ω
VCC(+3.3 V)
10 nF
130
Ω
SD
82
Ω
LVTTL
82
Ω
82
Ω
LVPECL
RD-
Z = 50
Ω
Z = 50
Ω
Note:
C1 = C2 = C3 = 10 nF or 100 nF
* Loading R1 is optional.
TERMINATE AT DEVICE INPUTS
Figure 4. Alternative Termination Circuits
5
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