EEWORLDEEWORLDEEWORLD

Part Number

Search

IS46LD32128A-18BLA2

Description
DDR DRAM, 128MX32, CMOS, PBGA134, FBGA-134
Categorystorage    storage   
File Size7MB,143 Pages
ManufacturerIntegrated Silicon Solution ( ISSI )
Download Datasheet Parametric Compare View All

IS46LD32128A-18BLA2 Overview

DDR DRAM, 128MX32, CMOS, PBGA134, FBGA-134

IS46LD32128A-18BLA2 Parametric

Parameter NameAttribute value
MakerIntegrated Silicon Solution ( ISSI )
package instructionBGA,
Reach Compliance Codeunknow
ECCN codeEAR99
Date Of I2016-06-15
access modeMULTI BANK PAGE BURST
Other featuresSELF REFRESH; IT ALSO REQUIRES 1.8V NOM
JESD-30 codeR-PBGA-B134
memory density4294967296 bi
Memory IC TypeDDR DRAM
memory width32
Number of functions1
Number of ports1
Number of terminals134
word count134217728 words
character code128000000
Operating modeSYNCHRONOUS
organize128MX32
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Package shapeRECTANGULAR
Package formGRID ARRAY
self refreshYES
Maximum supply voltage (Vsup)1.3 V
Minimum supply voltage (Vsup)1.14 V
Nominal supply voltage (Vsup)1.2 V
surface mountYES
technologyCMOS
Terminal formBALL
Terminal locationBOTTOM
IS43/46LD16256A
IS43/46LD32128A
4Gb (x16, x32) Mobile LPDDR2 S4 SDRAM
FEATURES
Low-voltage Core and I/O Power Supplies
VDD2 = 1.14-1.30V, VDDCA/VDDQ = 1.14-1.30V,
VDD1 = 1.70-1.95V
High Speed Un-terminated Logic(HSUL_12) I/O
Interface
Clock Frequency Range : 10MHz to 533MHz
(data rate range : 20Mbps to 1066Mbps per I/O)
Four-bit Pre-fetch DDR Architecture
Multiplexed, double data rate, command/ad-
dress inputs
Eight internal banks for concurrent operation
Bidirectional/differential data strobe per byte of
data (DQS/DQS#)
Programmable Read/Write latencies(RL/WL)
and burst lengths(4,8 or 16)
ZQ Calibration
On-chip temperature sensor to control self re-
fresh rate
Partial –array self refresh(PASR)
Deep power-down mode(DPD)
Operation Temperature
Commercial (T
C
= 0°C to 85°C)
Industrial (T
C
= -40°C to 85°C)
Automotive, A1 (T
C
= -40°C to 85°C)
Automotive, A2 (T
C
= -40°C to 105°C)
ADVANCED INFORMATION
AUGUST 2016
DESCRIPTION
The IS43/46LD16256A/32128A is 4Gbit CMOS
LPDDR2 DRAM. The device is organized as 8 banks
of 32Meg words of 16bits or 16Meg words of 32bits.
This product uses a double-data-rate architecture to
achieve high-speed operation. The double data rate
architecture is essentially a 4N prefetch architecture
with an interface designed to transfer two data words
per clock cycle at the I/O pins. This product offers fully
synchronous operations referenced to both rising and
falling edges of the clock. The data paths are internally
pipelined and 4n bits prefetched to achieve very high
bandwidth.
ADDRESS TABLE
Parameter
Row Addresses
Column Addresses
Bank Addresses
Refresh Count
128Mx32
R0-R13
C0-C9
BA0-BA2
8192
256Mx16
R0-R13
C0-C10
BA0-BA2
8192
KEY TIMING PARAMETERS
Speed
Grade
-18
-25
-3
Data
Rate
(Mb/s)
1066
800
667
Write
Read tRCD/
Latency Latency tRP
4
3
2
8
6
5
Typical
Typical
Typical
OPTIONS
Configuration:
− 256Mx16 (32M x 16 x 8 banks)
− 128Mx32 (16M x 32 x 8 banks)
Package:
− 134-ball BGA for x16 / x32
− 168-ball PoP BGA for x32
Note:
Other clock frequencies/data rates supported; please
refer to AC timing tables.
Copyright © 2016 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex-
pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon
Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00B
08/17/2016
1

IS46LD32128A-18BLA2 Related Products

IS46LD32128A-18BLA2 IS46LD32128A-18BPLA2 IS46LD32128A-25BPLA2
Description DDR DRAM, 128MX32, CMOS, PBGA134, FBGA-134 DDR DRAM, 128MX32, CMOS, PBGA168, FBGA-168 DDR DRAM, 128MX32, CMOS, PBGA168, FBGA-168
Maker Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI )
package instruction BGA, VFBGA, VFBGA,
Reach Compliance Code unknow compliant compliant
access mode MULTI BANK PAGE BURST MULTI BANK PAGE BURST MULTI BANK PAGE BURST
Other features SELF REFRESH; IT ALSO REQUIRES 1.8V NOM SELF REFRESH; IT ALSO REQUIRES 1.8V NOM SELF REFRESH; IT ALSO REQUIRES 1.8V NOM
JESD-30 code R-PBGA-B134 S-PBGA-B168 S-PBGA-B168
memory density 4294967296 bi 4294967296 bit 4294967296 bit
Memory IC Type DDR DRAM DDR DRAM DDR DRAM
memory width 32 32 32
Number of functions 1 1 1
Number of ports 1 1 1
Number of terminals 134 168 168
word count 134217728 words 134217728 words 134217728 words
character code 128000000 128000000 128000000
Operating mode SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
organize 128MX32 128MX32 128MX32
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code BGA VFBGA VFBGA
Package shape RECTANGULAR SQUARE SQUARE
Package form GRID ARRAY GRID ARRAY, VERY THIN PROFILE, FINE PITCH GRID ARRAY, VERY THIN PROFILE, FINE PITCH
self refresh YES YES YES
Maximum supply voltage (Vsup) 1.3 V 1.3 V 1.3 V
Minimum supply voltage (Vsup) 1.14 V 1.14 V 1.14 V
Nominal supply voltage (Vsup) 1.2 V 1.2 V 1.2 V
surface mount YES YES YES
technology CMOS CMOS CMOS
Terminal form BALL BALL BALL
Terminal location BOTTOM BOTTOM BOTTOM
Is it Rohs certified? - conform to conform to
length - 12 mm 12 mm
Peak Reflow Temperature (Celsius) - NOT SPECIFIED NOT SPECIFIED
Maximum seat height - 0.95 mm 0.95 mm
Terminal pitch - 0.5 mm 0.5 mm
Maximum time at peak reflow temperature - NOT SPECIFIED NOT SPECIFIED
width - 12 mm 12 mm

Technical ResourceMore

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 306  513  1100  159  1155  7  11  23  4  24 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号