DATA SHEET
SXT6051
STM-1/0 SDH Overhead Terminator
General Description
The SXT6051 Overhead Terminator implements the
Regenerator Section Termination, Multiplexer Section
Termination and Higher Order Path Termination in STM-0
(51Mb/s) and STM-1 (155mB/s) multiplexers. It provides
micro-controller access for performance monitoring, alarm
detection and configuration for transmit and receive paths.
When used with the SXT6251 (21E1 Mapper), a complete
solution for a 21 E1 or a 63 E1 Multiplexer is created.
The SXT6051 is compliant with the latest releases of ITU-
T G.703 and G.707. It provides all the alarm and control
features to easily implement the multiplexer described in
ITU-T G.783.
MAY 1998
Revision 1.1
Features
• Performs Regenerator Section, Multiplexer Section,
and Higher Order Path Overhead Processing for
STM-1 and STM-0 signals.
• Byte parallel interface for STM-1 or STM-0, with
byte alignment performed internally. Serial NRZ or
B3ZS interface option for STM-0.
• Demultiplexes STM-0/STM-1 signals to Telecom Bus
output with optional pointer processor re-timing.
• Multiplexes Telecom Bus data into STM-0 or STM-1
signals with pointer processing.
• Compatible with 1+1 protected ITU architecture.
• Records all RSOH, MSOH, and HPOH alarms. One
second counters for B1, B2, B3, M1 REI and G1 REI.
• Full J0/J1 trace identifier processing
• Serial access to STM-1 user-defined, media-depen-
dent and national bytes.
• Dedicated pins for serial access or pass-through fea-
ture for E1, E2, F1, F2, F3, D1-D3 & D4-D12 bytes.
• Low power CMOS technology with 3.3V core and 5V
I/O in PQFP-208 package.
• IEEE 1149.1 Boundary Scan (JTAG) support.
Applications
• SDH Terminal Mux/ADM for microwave radio
• ADM fiber ring Mux
• Digital Loop Carrier (NGDLC) Systems
• Digital Cross-Connect System
SXT6051 System Block Diagram
S ETS
SXT 6051
O HT
TX
TB us T im ing
6.48M /19.44M C lock
Telecom B us D ata
4
POH
S erial A ccesses
MMSP
B us
SOH
S erial A ccesses
Transm it
M aster
C lock In
Tx C lock out
D ata
1 o r 8 (S T M -0 )
8 (S T M -1 )
Tran sm it
Teleco m
B us Ad d
Interface
AU -3/4 &
V C -3/4
Tran sm it P ro cessor
(H P T, M SA(P P))
S TM -0 / S TM -1
Tran sm it S ectio n
Term ination &
P ro tection Fu nction
(R S T, M ST, M S P)
SXT 6251
21 Channel
M apper
Telecom B us D ata
6.48M /19.44M C lock
TB us T im ing
R eceive
Teleco m
B us
D rop
Interface
M icrocontroller Interface (Intel/M otorola selectable)
D ata
C lock
LO S
1 o r 8 (S T M -0 )
8 (S T M -1 )
S TM -0 /1
Line
Interface
AU -3/4 &
V C -3/4
R eceive P ro cessor
(M S A,H PT& R etim ing )
S TM -0 / S TM -1
R eceive S ection
Term ination &
P ro tection Fu nction
(R S T, M ST, M S P)
RX
4
optional retim ing
C lock&tim ing
POH
S erial A ccesses
DMSP
B us
SOH
S erial A ccesses
SXT6051 STM-1/0 SDH Overhead Terminator
Table Of Contents
Pin Assignments And Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Transmit Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Receive Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Reference Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Chip Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Repeater Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Terminal Mode Configuration (No Protection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Side Telecom Bus Timing Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Side Telecom Bus Timing Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Add and Drop Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Side Telecom Bus Timing Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Side Telecom Bus Timing Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Updating the Transmit AU Pointer Justification Event Counters . . . . . . . . . . . . . .
Terminal Protection Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Side Telecom Bus Timing Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Side Telecom Bus Timing Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver Default Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Distribution and Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Framer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Regenerator Section Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiplexer Section Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiplexer Section Protection (MSP) Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pointer Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Higher Order Path Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Re-Timing Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitter Default Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Higher Order Path Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Pointer Processing Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Multiplex Section Protection (MSP Block) . . . . . . . . . . . . . . . . . . . . . . .
Multiplexer Section Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Regenerator Section Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Distribution and Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
21
22
22
22
24
24
24
25
25
25
25
25
25
25
27
27
28
29
30
31
31
32
32
32
34
35
35
36
38
38
38
Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Transmit Frame Parallel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2
SXT6051
Transmit Frame Serial Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Receive Re-timing Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Telecom Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Multiplexer Telecom Bus Terminal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Multiplexer Telecom Bus ADM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Demultiplexer Telecom Bus (Terminal or ADM) Mode. . . . . . . . . . . . . . . . . . . . . . . . . . 47
Protection Bus Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Transmitter “Master” in 1+1 Protection Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitter “Slave” in 1+1 Protection Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive”Master” in 1+1 Protection Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive “Slave” Configuration (1+1 Protection). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
F2 and F3 Digital Channel Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit side access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive side access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E1, E2 and F1 Orderwire Channel Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPOH Bytes Serial Access Functional Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit serial HPOH Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Serial HPOH Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOH Overhead Access Functional Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Side SOH Serial Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Side SOH Serial Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D1 to D3 Data Communication Channel Functional Timing. . . . . . . . . . . . . . . . . . . . . .
Transmit Side Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Side Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D4 to D12 Data Communication Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Side Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Side Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
51
51
52
52
55
55
55
56
56
56
57
57
58
59
59
60
61
61
61
62
62
62
OverHead Byte Access Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
BIP Receive Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Microprocessor Interface & Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Intel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Motorola interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Clearing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Status Registers Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C2, K3, K2, K1 and S1 Receive Byte Registers Access . . . . . . . . . . . . . . . . . . . .
Counter Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
82
82
82
82
82
83
83
83
83
3
SXT6051 STM-1/0 SDH Overhead Terminator
Register Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Global Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
OCR1—Operational Configuration 1 (50H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCR2—Operational Configuration 2 (51H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CHIP_ID—Chip ID Number (52H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BUF_ACNTS—Buffer All Counters (54H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R_RSTC1—Receive RST Configuration 1 (40H). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R_RSTC2—Receive RST Configuration 2 (47H). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LOF_LMN—Loss of Frame L, M, & N Configuration (41–42H) . . . . . . . . . . . . . . . . . . .
OOF_ECNT—Out Of Frame Event Counter (44–43H) . . . . . . . . . . . . . . . . . . . . . . . . .
B1_ERRCNT—B1 Error Counter (46–45H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
J0_RSTR_C—J0 Expected String Control (0EH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
J0_RSTR_D—J0 Expected String Data (0FH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WINSZ_SB2—Window Size for Setting ExcB2ErrSt (1C–1BH) . . . . . . . . . . . . . . . . . .
CWIN_SB2—Consecutive Windows for Setting ExcB2ErrSt (1DH) . . . . . . . . . . . . . . .
E#_EXCWIN—Number of Errs/Win for Excessively Errored Window (1EH) . . . . . . . . .
WINSZ_C2—Window Size for Clearing ExcB2ErrSt (16–15H) . . . . . . . . . . . . . . . . . . .
CWIN_CB2—Consecutive Windows for Clearing ExcB2ErrSt (17H) . . . . . . . . . . . . . .
E#_NEXCWIN—Number of Errs/Win for Non-Excessively Errored Window (18H) . . . .
B2_BLKCNT—B2 Block Error Counter (11–10H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B2_BIPCNT—B2 BIP Error Counter (14–12H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR_BLKCNT—MST REI Block Error Counter (0A–09H) . . . . . . . . . . . . . . . . . . . . . . .
MR_BIPCNT—MST REI BIP Error Counter (0D–0BH) . . . . . . . . . . . . . . . . . . . . . . . . .
R_K1—Received K1 byte (00H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R_K2—Received K2 Byte (01H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R_S1—Received S1 byte (02H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R_NU1_8—Received Nu1_8 byte (03H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R_NU1_9—Received Nu1_9 byte (04H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R_NU2_8—Received Nu2_8 byte (05H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R_NU2__9—Received Nu2_9 byte (06H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R_NU9_8—Received Nu9_8 byte (07H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R_NU9_9—Received Nu9_9 byte (08H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R_MSP_C—Receive MSP Configuration (20H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R_MSP_OP—Receive MSP Operational (21H). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R_PROTK1—Received K1 byte on Protection Bus from Slave (22H). . . . . . . . . . . . .
R_PROTK2—Received K2 byte on Protection Bus from Slave (23H). . . . . . . . . . . . .
89
90
91
91
92
93
93
94
94
95
95
96
96
96
96
97
97
97
97
98
98
98
98
98
99
99
99
99
99
99
Receive Regenerator Section Termination Registers . . . . . . . . . . . . . . . . . . . . . . . . 92
Receive Regenerator and Multiplexer Section Termination Registers . . . . . . . . . . . 95
Receive Multiplexer Section Protection Registers . . . . . . . . . . . . . . . . . . . . . . . . . 100
100
100
101
101
Receive Multiplexer Section Adaptation Registers . . . . . . . . . . . . . . . . . . . . . . . . . 101
R_MSA_C—Receive MSA Configuration (90H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
R_AU_NCNT—Receive Negative AU Pointer Justification Event Counter (92–91H) . 102
R_AU_PCNT—Receive Positive AU Pointer Justification Event Counter (94–93H) . . 102
Receive HighOrder Path Termination Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4
SXT6051
R_HPT_C1—Receive HPT Configuration 1 Register (80H) . . . . . . . . . . . . . . . . . . . .
R_HPT_C2—Receive HPT Configuration 2 Register (81H) . . . . . . . . . . . . . . . . . . . .
J1_RSTR_C—J1 Expected String Control Register (8AH) . . . . . . . . . . . . . . . . . . . . .
J1_RSTR_D—J1 Expected String Data Register (8BH) . . . . . . . . . . . . . . . . . . . . . . .
EXP_C2—Expected C2 byte Register (82H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R_C2—Received C2 byte Register (83H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R_K3—Received K3 byte Register (84H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R_HPT_RDI—Received HPT RDI Bits Register (85H) . . . . . . . . . . . . . . . . . . . . . . . .
B3_ECNT—B3 Error Event Counter (87–86H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPTREI_CNT—HPT REI Counter (89–88H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T_RMST_OP1—Transmit RMST Operational 1 Register (30H) . . . . . . . . . . . . . . . . .
T_RMST_OP2—Transmit RMST Operational 2 Register (1AH) . . . . . . . . . . . . . . . . .
T_SC1_SOH—Transmit Source Configuration 1 for SOH bytes Register (60H) . . . . .
T_SC2_SOH—Transmit Source Configuration 2 for SOH bytes Register (61H) . . . . .
T_SC3_SOH—Transmit Source Configuration 3 for SOH Bytes Register (62H). . . . .
T_SC4_SOH—Transmit Source Configuration 4 for SOH Bytes Register (63H). . . . .
J0_TSTR_C—J0 Transmit String Control Register (3AH) . . . . . . . . . . . . . . . . . . . . . .
JO_TSTR_D—J0 Transmit String Data Register (3BH) . . . . . . . . . . . . . . . . . . . . . . .
MP_TNU1_8—Microprocessor Provided Transmit Nu1_8 Byte (31H) . . . . . . . . . . . .
MP_TNU1_9—Microprocessor Provided Transmit Nu1_9 Byte Register (32H) . . . . .
MP_TNU2_8—Microprocessor Provided Transmit Nu2_8 Byte (33H) . . . . . . . . . . . .
MP_TNU2_9—Microprocessor Provided Transmit Nu2_9 Byte Register (34H) . . . . .
MP_TNU9_8—Microprocessor Provided Transmit Nu9_8 Byte (35H) . . . . . . . . . . . .
MP_TNU9_9—Microprocessor Provided Transmit Nu9_9 Byte (36H) . . . . . . . . . . . .
MP_TK1—Microprocessor Provided Transmit K1 Byte Register (37H) . . . . . . . . . . . .
MP_TK2—Microprocessor Provided Transmit K2 Byte Register (38H) . . . . . . . . . . . .
MP_TS1—Microprocessor Provided Transmit S1 Byte Register (39H) . . . . . . . . . . . .
103
104
105
105
105
105
105
106
106
106
107
108
109
110
111
112
113
114
114
114
114
114
115
115
115
115
115
Transmit Regenerator and Multiplexer Section Termination Registers . . . . . . . . . . 107
Transmit Multiplexer Section Adaptation Registers . . . . . . . . . . . . . . . . . . . . . . . . . 116
T_AU_NCNT—Transmit Negative AU Pointer Justification Event Counter (E3–E2H) 116
T_AU_PCNT—Transmit Positive AU Pointer Justification Event Counter (E5–E4H) . 116
Transmit HighOrder Path Termination Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 117
T_SC_HPOH—Transmit Source Configuration for HPOH bytes (70H) . . . . . . . . . . . .
T_HPT_C—Transmit HPT Configuration (71H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MP_TC2—Microprocessor Provided Transmit C2 Byte (72H) . . . . . . . . . . . . . . . . . . .
MP_TK3—Microprocessor Provided Transmit K3 Byte (73H) . . . . . . . . . . . . . . . . . . .
J1_TSTR_C—J1 Transmit String Control (75H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
J1_TSTR_D—J1 Transmit String Data (76H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IS_RG—Receive Regenerator Section Interrupt Source (A0H). . . . . . . . . . . . . . . . . .
IS_RGMUX—Receive Regenerator and Multiplexor Section Interrupt Source (A1H) .
IS_MUX—Receive Multiplexor Section Interrupt Source (A2H). . . . . . . . . . . . . . . . . .
IS_PROT—Receive Protection Section Interrupt Source (A3H) . . . . . . . . . . . . . . . . .
IS_A_HPT—Receive Adaptation and HPT Interrupt Source (A4H) . . . . . . . . . . . . . . .
IS_HPT—Receive HPT Interrupt Source (A5H). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
117
118
119
119
120
120
121
121
122
122
123
123
Interrupt Source Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5
京公网安备 11010802033920号
EEWORLD
