HI-3593
August 2013
3.3V ARINC 429 Dual Receiver,
Single Transmitter with SPI Interface
PIN CONFIGURATIONS
(Top View)
VDD
VDD
CP-
CP+
V+
GND
GND
CN+
CN-
V-
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
GENERAL DESCRIPTION
The HI-3593 from Holt Integrated Circuits is a CMOS
integrated circuit for interfacing a Serial Peripheral
Interface (SPI) enabled microcontroller to the ARINC 429
serial bus. The device provides two receivers, each with
user-programmable label recognition for any combination
of 256 possible labels, 32 x 32 Receive FIFO, 3 priority-
label quick-access double-buffered registers and analog
line receiver. The independent transmitter has a 32 x 32
Transmit FIFO and built-in line driver. The line driver
operates from a single 3.3V supply and includes on-chip
DC/DC converter to generate the bipolar ARINC 429
differential voltage levels needed to directly drive the
ARINC 429 bus. The status of the transmit and receive
FIFOs and priority-label buffers can be monitored using
the programmable external interrupt pins, or by polling the
HI-3593 Status Registers. Other features include a
programmable option of data or parity in the 32nd bit, and
the ability to switch the bit-signifiance of ARINC 429 labels.
Pins are available with different input resistance and
output resistance values which provides flexibility when
using external lightning protection circuitry.
The Serial Peripheral Interface minimizes the number of
host interface signals resulting in a small footprint device
that can be interfaced to a wide range of industry-standard
microcontrollers supporting SPI. Alternatively, the SPI
signals may be controlled using just four general purpose
I/O port pins from a microcontroller or custom FPGA. The
SPI and all control signals are CMOS and TTL compatible
and support 3.3V operation.
The HI-3593 applies the ARINC 429 protocol to the
receivers and transmitter. ARINC 429 databus timing
comes from a 1 MHz clock input, or an internal counter can
derive it from higher clock frequencies having certain fixed
values, possibly the external host processor clock.
-
-
-
-
-
-
-
-
-
-
-
RIN1A-40
RIN1A
RIN1B
RIN1B-40
RIN2A-40
RIN2A
RIN2B
RIN2B-40
MR
ACLK
- 1
- 2
- 3
- 4
- 5
- 6
- 7
- 8
- 9
- 10
- 11
HI-3593PCI
HI-3593PCT
HI-3593PCM
-
-
-
-
-
-
-
-
-
-
-
AMPA
TXAOUT
AMPB
TXBOUT
TFULL
TEMPTY
R1FLAG
R1INT
R2FLAG
R2INT
44 - Pin Plastic 7mm x 7mm
Chip-Scale Package (QFN)
FEATURES
·
·
·
·
·
·
·
·
ARINC 429 specification compliant
On-chip analog line driver and receiver connect
directly to ARINC 429 bus
Programmable label recognition for 256 labels
32 x 32 Receive FIFOs and Priority-Label buffers
Independent data rates for Transmit and Receive
10MHz, four-wire Serial Peripheral Interface (SPI)
Industrial & extended temperature ranges
Single 3.3V power supply
-1
RIN1A-40 - 2
RIN1A - 3
RIN1B - 4
RIN1B-40 - 5
RIN2A-40 - 6
RIN2A - 7
RIN2B - 8
RIN2B-40 - 9
MR - 10
ACLK - 11
44
43
42
41
40
39
38
37
36
35
34
- VDD
- VDD
- CP-
- CP+
- V+
- GND
- GND
- CN+
- CN-
- V-
-
CS
SI
SCK
SO
GND
MB1-1
MB1-2
MB1-3
MB2-1
MB2-2
MB2-3
-
-
-
-
-
-
-
-
-
-
-
12
13
14
15
16
17
18
19
20
21
22
HI-3593PQI
HI-3593PQT
HI-3593PQM
33 - AMPA
32 - TXAOUT
31 - AMPB
30 - TXBOUT
29 -
28 - TFULL
27 - TEMPTY
26 - R1FLAG
25 - R1INT
24 - R2FLAG
23 - R2INT
44 - Pin Plastic Quad Flat Pack (PQFP)
(DS3593 Rev. B)
HOLT INTEGRATED CIRCUITS
www.holtic.com
CS - 12
SI - 13
SCK - 14
SO - 15
GND - 16
MB1-1 - 17
MB1-2 - 18
MB1-3 - 19
MB2-1 - 20
MB2-2 - 21
MB2-3 - 22
08/13
HI-3593
BLOCK DIAGRAM
VDD (3.3V)
Transmitter
ARINC 429
Line Driver
V+
5W
AMPA
ARINC 429
Transmit
Data FIFO
ARINC 429
Transmit
Formatter
37.5W
TXAOUT
TXBOUT
37.5W
AMPB
5W
V-
TFULL
MR
Transmit Status
Transmit Control
TEMPTY
V+
SCK
CS
SI
SO
3.3V
ACLK
ARINC
Clock
Divider
DC / DC
Converter
SPI
Interface
V-
V+
47uF
V-
47uF
CP+
CP-
CN+
CN-
2.2uF
0.47uF
Receiver 2
Receiver 1
R2FLAG
Receive Status
RIN2A
RIN2B
RIN2B-40
RIN2A-40
RIN1A
RIN1B
RIN1B-40
RIN1A-40
Priority -
Label
Match (x3)
40 KW
40 KW
Receive Control
Label
Filter
Bit Map
Memory
R2INT
Flag /
Interrupt
R1FLAG
R1INT
ARINC 429
Line Receiver
ARINC 429
Valid word
Checker
(See fig. 3)
Label
Filter
ARINC 429
Received
Data FIFO
(32 x 32)
Buffer
Buffer
Buffer
P-L Reg 3
P-L Reg 2
P-L Reg 1
MB2-3
MB2-2
MB2-1
MB1-3
MB1-2
MB1-1
GND
HOLT INTEGRATED CIRCUITS
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HI-3593
PIN DESCRIPTIONS
SIGNAL
RIN1A-40
RIN1A
RIN1B
RIN1B-40
RIN2A-40
RIN2A
RIN2B
RIN2B-40
MR
ACLK
CS
SI
SCLK
SO
GND
MB1-1
MB1-2
MB1-3
MB2-1
MB2-2
MB2-3
R2INT
R2FLAG
R1INT
R1FLAG
TEMPTY
TFULL
TXBOUT
AMPB
TXAOUT
AMPA
V-
CN-
CN+
V+
CP-
CP+
VDD
FUNCTION
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
OUTPUT
POWER
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
CONVERTER
CONVERTER
CONVERTER
CONVERTER
CONVERTER
CONVERTER
POWER
DESCRIPTION
Alternate ARINC receiver 1 positive input. Requires external 40K ohm resistor
ARINC receiver 1 positive input. Direct connection to ARINC 429 bus
ARINC receiver 1 negative input. Direct connection to ARINC 429 bus
Alternate ARINC receiver 1 negative input. Requires external 40K ohm resistor
Alternate ARINC receiver 2 positive input. Requires external 40K ohm resistor
ARINC receiver 2 positive input. Direct connection to ARINC 429 bus
ARINC receiver 2 negative input. Direct connection to ARINC 429 bus
Alternate ARINC receiver 2 negative input. Requires external 40K ohm resistor
Master Reset. A positive pulse clears Receive and Transmit data FIFOs and flags
Master timing source for the ARINC 429 receiver and transmitter
Chip Select. Data is shifted into SI and out of SO when CS is low.
SPI interface serial data input
SPI Clock. Data is shifted into or out of the SPI interface using SCK
SPI interface serial data output
Chip 0V supply
Goes high when Receiver 1, Priority-Label Mail Box 1 contains a message
Goes high when Receiver 1, Priority-Label Mail Box 2 contains a message
Goes high when Receiver 1, Priority-Label Mail Box 3 contains a message
Goes high when Receiver 2, Priority-Label Mail Box 1 contains a message
Goes high when Receiver 2, Priority-Label Mail Box 2 contains a message
Goes high when Receiver 2, Priority-Label Mail Box 3 contains a message
Receiver 2 programmable Interrupt pin
Goes high as defined by Flag / Interrupt Assignment Register
Receiver 1 programmable Interrupt pin
Goes high as defined by Flag / Interrupt Assignment Register
Goes high when the Transmit FIFO is empty
Goes high when the Transmit FIFO contains the maximum 32 ARINC 429 words
ARINC line driver negative output. Direct connection to ARINC 429 bus
Alternate ARINC line driver negative output. Requires external 32.5 ohm resistor
ARINC line driver positive output. Direct connection to ARINC 429 bus
Alternate ARINC line driver positive output. Requires external 32.5 ohm resistor
DC/DC negative voltage output
DC/DC converter fly capacitor for V-
DC/DC converter fly capacitor for V-
DC/DC positive voltage output
DC/DC converter fly capacitor for V+
DC/DC converter fly capacitor for V+
Chip 3.3V supply
INTERNAL PULL UP / DOWN
50K ohm pull-down
50K ohm pull-down
50K ohm pull-up
50K ohm pull-down
50K ohm pull-down
INSTRUCTIONS
Instruction op codes are used to read, write and configure the HI-
3593. When CS goes low, the next 8 clocks at the SCK pin shift an
instruction op code into the decoder, starting with the first rising
edge. The op code is fed into the SI pin, most significant bit first.
For write instructions, the most significant bit of the data word must
immediately follow the instruction op code and is clocked into its
register on the next rising SCK edge. Data word length varies
depending on word type written: 8-bit Control Register writes, 32-
bit ARINC label writes or 256-bit writes to a channel’s label-
matching enable/disable memory.
SPI Instructions are of a common format. The first bit specifies
whether the instruction is a write “0” or read “1” transfer. The next
five bits specify the source or destination of the associated data
byte(s), and the last two bits are “don’t care”.
R
/W
Source /
Destination
X
X
0
LSB
For read instructions, the most significant bit of the requested data
word appears at the SO pin after the last op code bit is clocked into
the decoder, at the next falling SCK edge. As in write instructions,
the data field bit-length varies with read instruction type.
MSB
7
6
5
4
3
2
1
SPI INSTRUCTION FORMAT
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HI-3593
TABLE 1. DEFINED INSTRUCTIONS
Op-Code R/W
0x00
0x04
0x08
0x0C
0x10
0x14
W
W
W
W
W
W
# Data
bytes
0
0
1
4
1
32
DESCRIPTION
Instruction not implemented. No operation.
Software controlled Master Reset
Write Transmit Control Register
Write ARINC 429 message to Transmit FIFO
Write Receiver 1 Control Register
Write label values to Receiver 1 label memory. Starting with label 0xFF, consecutively set or reset each
label in descending order. For example, if the first data byte is programmed to 10110010 then labels FF,
FD FC and F9 will be set and FE, FB, FA and F8 will be reset.
Write Receiver 1 Priority-Label Match Registers. The data field consists of three eight-bit labels. The first data
byte is written to P-L filter #3, the second to P-L filter #2, and the last byte to filter #1
Write Receiver 2 Control Register
Write label values to Receiver 2 label memory. Starting with label 0xFF, consecutively set or reset each
label in descending order. For example, if the first data byte is programmed to 10110010 then labels FF,
FD FC and F9 will be set and FE, FB, FA and F8 will be reset.
Write Receiver 2 Priority-Label Match Registers. The data field consists of three eight-bit labels. The first
eight bits is written to P-L filter #3, the second to P-L filter #2, and the last byte to filter #1
Write Flag / Interrupt Assignment Register
Write ACLK Division Register
Transmit current contents of Transmit FIFO if Transmit Control Register bit 5 (TMODE) is a “0”
Software Reset. Clears the Transmit and Receive FIFOs and the Priority-Label Registers
Set all bits in Receiver 1 label memory to a “1”
Set all bits in Receiver 2 label memory to a “1”
Read Transmit Status Register
Read Transmit Control Register
Read Receiver 1 Status Register
Read Receiver 1 Control Register
Read label values from Receiver 1 label memory.
Read Receiver 1 Priority-Label Match Registers.
Read one ARINC 429 message from the Receiver 1 FIFO
Read Receiver 1 Priority-Label Register #1, ARINC429 bytes 2,3 & 4 (bits 9 - 32)
Read Receiver 1 Priority-Label Register #2, ARINC429 bytes 2,3 & 4 (bits 9 - 32)
Read Receiver 1 Priority-Label Register #3, ARINC429 bytes 2,3 & 4 (bits 9 - 32)
Read Receiver 2 Status Register
Read Receiver 2 Control Register
Read label values from Receiver 2 label memory.
Read Receiver 2 Priority-Label Match Registers.
Read one ARINC 429 message from the Receiver 2 FIFO
Read Receiver 2 Priority-Label Register #1, ARINC429 bytes 2,3 & 4 (bits 9 - 32)
Read Receiver 2 Priority-Label Register #2, ARINC429 bytes 2,3 & 4 (bits 9 - 32)
Read Receiver 2 Priority-Label Register #3, ARINC429 bytes 2,3 & 4 (bits 9 - 32)
Read Flag / Interrupt Assignment Register
Read ACLK Division Register
Instruction not implemented. No operation.
0x18
0x24
0x28
W
W
W
3
1
32
0x2C
0x34
0x38
0x40
0x44
0x48
0x4C
0x80
0x84
0x90
0x94
0x98
0x9C
0xA0
0xA4
0xA8
0xAC
0xB0
0xB4
0xB8
0xBC
0xC0
0xC4
0xC8
0xCC
0xD0
0xD4
0xFF
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
3
1
1
0
0
0
0
1
1
1
1
32
3
4
3
3
3
1
1
32
3
4
3
3
3
1
1
0
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HI-3593
REGISTER DESCRIPTIONS
R
FL
SD IP
9
SD
1
SD
0
O
PA N
R
LA ITY
B
PL
RE
O
C
R
N
AT
E
7 6
MSB
5
4
3
2
1
0
LSB
RECEIVE CONTROL REGISTER
(Receiver 1 Write, SPI Op-code 0x10)
(Receiver 1 Read, SPI Op-code 0x94)
(Receiver 2 Write, SPI Op-code 0x24)
(Receiver 2 Read, SPI Op-code 0xB4)
Bit Name
7
6
5
4
3
2
RFLIP
SD9
SD10
SDON
PARITY
LABREC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default Description
0
0
0
0
0
0
Setting this bit reverses the bit order of the first 8 bits of each ARINC 429 message received.
See figure 1 for details.
If the receiver decoder is enable by setting the SDON bit to a “1”, then ARINC 429 message
bit 9 must match this bit for the message to be accepted.
If the receiver decoder is enable by setting the SDON bit to a “1”, then ARINC 429 message
bit 10 must match this bit for the message to be accepted.
If this bit is set, bits 9 and 10 of the received ARINC 429 message must match SD9 and SD10
Received word parity checking is enabled when this bit is set. If “0”, all 32 bits of the received
ARINC 429 word are stored without parity checking.
When “0”, all received messages are stored. If this bit is set, incoming ARINC message label
filtering is enabled. Only messages whose corresponding label filter table entry is set to a “1”
will be stored in the Receive FIFO.
Priority-Label Register enable. If PLON = “1” the three Priority-Label Registers are enabled
and received ARINC 429 messages with labels that match one of the three pre-programmed
values will be capured and stored in the corresponding Prioty-Label Mail Boxes. If PLON = “0”
the Priority-Label matching feature is turned off and no words are placed in the mail boxes.
If RATE is “0”, ARINC 429 high-speed data rate is selected. RATE = “1” selects low-speed
ARINC 429 data rate (high-speed / 8).
1
PLON
R/W
0
0
RATE
R/W
0
TRANSMIT CONTROL REGISTER
IZ
LI
TM
P
O
SE
DE
L
O
FTE
D
D
S
TP EV
T
A EN
X
RIT
Y
5
4
3
2
1
(Write, SPI Op-code 0x08)
(Read, SPI Op-code 0x84)
7 6
MSB
0
LSB
Bit Name
7
6
5
HIZ
TFLIP
TMODE
R/W
R/W
R/W
R/W
Default Description
0
0
0
Setting this bit puts the on-chip line driver outputs to a high-impedance state.
Setting this bit reverses the bit order of the first 8 bits of each ARINC 429 message transmitted.
See figure 1 for details.
If TMODE is “0”, data in the transmit FIFO is sent to the ARINC 429 bus only upon receipt of an
SPI op-code 0x40, transmit enable, command. If TMODE is a “1”, data is sent as soon as it is
available.
Setting SELFTEST causes an internal connection to be made looping-back the transmitter
outputs to both receiver inputs for self-test purposes. When in self-test mode, the HI-3593
ignores data received on the two ARINC 429 receive channels and holds the on-chip line driver
outputs in the NULL state to prevent self-test data being transmitted to other receivers on the
bus.
If the TPARITY bit is set, the transmitter inserts an odd parity bit if ODDEVEN = “0”, or an even if
ODDEVEN = “1”.
If TPARITY = “0”, no parity bit is inserted and the 32nd transmitted bit is data. When TPARITY is
a “1” a parity bit is substituted for bit 32 according to the ODDEVEN bit value.
Not used.
If RATE is “0”, ARINC 429 high-speed data rate is selected. RATE = “1” selects low-speed
ARINC 429 data rate (high-speed / 8).
4
SELFTEST
R/W
0
3
2
1
0
ODDEVEN
TPARITY
X
RATE
R/W
R/W
R/W
R/W
0
0
0
0
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R
AT
E
TF
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