LC5128B-5T128C datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Programmable logic devices> Programmable logic> LC5128B-5T128C

LC5128B-5T128C: DescriptionEE PLD, 6.5ns, 128-Cell, CMOS, PQFP128, TQFP-128; CategoryProgrammable logic devices Programmable logic; File Size240KB，66 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com

Download Datasheet Parametric View All

LC5128B-5T128C Overview

EE PLD, 6.5ns, 128-Cell, CMOS, PQFP128, TQFP-128

LC5128B-5T128C Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Lattice
Parts packaging code	QFP
package instruction	TQFP-128
Contacts	128
Reach Compliance Code	_compli
Other features	YES
maximum clock frequency	142 MHz
In-system programmable	YES
JESD-30 code	S-PQFP-G128
JESD-609 code	e0
JTAG BST	YES
length	14 mm
Humidity sensitivity level	3
Dedicated input times
Number of I/O lines	92
Number of macro cells	128
Number of terminals	128
organize	0 DEDICATED INPUTS, 92 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP128,.64SQ,16
Package shape	SQUARE
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	240
power supply	2.5 V
Programmable logic type	EE PLD
propagation delay	6.5 ns
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage	2.7 V
Minimum supply voltage	2.3 V
Nominal supply voltage	2.5 V
surface mount	YES
technology	CMOS
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.4 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	14 mm

Preview

Download Datasheet

View All

ispMACH 5000B Family

Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability.

www.latticesemi.com/sales/discontinueddevicessales.cfm

2.5V In-System Programmable

SuperWIDE

High Density PLDs

September 2003

Data Sheet

Features

■

High Speed Logic Implementation

• SuperWIDE 68-input logic block

• Up to 35 product terms per output

• Single-level Global Routing Pool (GRP)

■

Easy System Integration

• 2.5V power supply

• Hot socketing

• Input pull-up, pull-down or Bus-keeper

(Pin-by-pin selectable)

• Open drain capability

• Macrocell-based power management

• IEEE 1149.1 Boundary Scan testable

• IEEE 1532 compliant In-System Programmable

(ISP™)

■

sysIO

Capability

•

LVCMOS 1.8, 2.5 and 3.3

LVTTL

SSTL 2 (I and II)

SSTL 3 (I and II)

CTT 3.3, CTT 2.5

HSTL (I and III)

PCI 3.3

GTL+

AGP-1X

LVDS (clock input)

LVPECL (clock input)

Programmable drive strength

ispMACH 5000B Introduction

The ispMACH 5000B represents the next generation of

Lattice’s SuperWIDE CPLD architecture. Through their

wide 68-input blocks, these devices give signiﬁcantly

improved speed performance for typical designs over

architectures with a lower number of inputs.

In addition to the unique beneﬁts of the SuperWIDE

architecture, the ispMACH 5000B provides sysIO capa-

bility to provide support for a variety of advanced I/O

standards.

The ispMACH 5000B devices consist of multiple Super-

WIDE 68-input, 32-macrocell Generic Logic Blocks

(GLBs) interconnected by a single-level routing system

referred to as the Global Routing Pool (GRP). Figure 1

shows the ispMACH 5000B block diagram. Together,

the GLBs and the GRP allow designers to create large

designs in a single device without compromising perfor-

mance.

■

Ease of Design

• Product term sharing

• Extensive clocking and OE capability

■

Broad Device Offering

• 128 to 512 macrocells

• 92 to 256 I/Os

• 128 to 484 pins/balls in TQFP, PQFP and fpBGA

packages

• Commercial and industrial temperature ranges

Table 1. ispMACH 5000B Family Selection Guide

ispMACH

5128B

Macrocells

User I/O Options

(ns)

– Set-up with 0 Hold (ns)

(ns)

MAX

(MHz)

Supply Voltage (V)

Package

128

3.0

1.7

2.2

275

2.5

128-pin TQFP

ispMACH

5256B

256

92/144

4.0

2.1

2.7

250

2.5

128-pin TQFP

208-pin PQFP

256-ball fpBGA

ispMACH

5384B

384

156/186

4.0

2.1

2.7

250

2.5

208-pin PQFP

256-ball fpBGA

ispMACH

5512B

512

156/196/256

4.5

2.5

2.8

200

2.5

208-pin PQFP

256-ball fpBGA

484-ball fpBGA

www.latticesemi.com

5kb_11.1

Lattice Semiconductor

Figure 1. Functional Block Diagram

I/O Bank 0

ispMACH 5000B Family Data Sheet

Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability.

www.latticesemi.com/sales/discontinueddevicessales.cfm

I/O Bank 3

VCCO0

VREF0

GCLK0

Generic

Logic

Block

Global Routing Pool

Generic

Logic

Block

VCCO3

VREF3

GCLK3

TDI

TDO

TMS

TCK

TOE

GCLK1

VCCO1

VREF1

Generic

Logic

Block

Generic

Logic

Block

GCLK2

VCCO2

VREF2

RESETB

GOE1

GOE2

I/O Bank 1

I/O Bank 2

The GLB has 68 inputs coming from the GRP and contains 163 product terms. These product terms form groups of ﬁve

product term clusters, which feed the product term sharing array and the macrocell directly. The ispMACH 5000B allows

up to 35 product terms to be connected to a single macrocell via the Product Term Sharing Array. The macrocell is

designed to provide ﬂexible clocking and control functionality with the capability to select between global, product

term, and block-level resources. The outputs of the macrocells are fed back into the switch matrices and, if

required, the sysIO cell.

All I/Os in the ispMACH 5000B family are sysIO capable, which are split into four banks. Each bank has a separate

I/O power supply and reference voltage. The sysIO cells allow operation with a wide range of today's emerging

interface standards. Within a bank, inputs can be set to a variety of standards providing the reference voltage

requirements of the chosen standards are compatible. Within each bank, the outputs can be set to differing stan-

dards providing the I/O power supply requirements of the chosen standard are compatible. Support for this wide

range of standards allows designers to achieve signiﬁcantly higher board-level performance compared to the more

traditional LVCMOS standards. Table 1 shows the key attributes and packages for the ispMACH5000B devices.

ispMACH 5000B Architecture

The ispMACH 5000B Family of In-System Programmable (ISP™) high density programmable logic devices is

based on Generic Logic Blocks (GLBs) and a global routing pool (GRP) structure interconnecting the GLBs.

Outputs from the GLBs drive the GRP. Enhanced switching resources are provided to allow signals in the GRP to

drive any or all of the GLBs. This mechanism allows fast, efﬁcient connections across the entire device. Figure 1

shows the basic ispMACH 5000B architecture.

Generic Logic Block

Each GLB contains 32 macrocells and a fully populated, programmable AND-array with 160 logic product terms

and three GLB-level control product terms. The GLB has 68 inputs from the GRP, which are available in both true

Lattice Semiconductor

Macrocell

ispMACH 5000B Family Data Sheet

Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability.

www.latticesemi.com/sales/discontinueddevicessales.cfm

The 32 registered macrocells in the GLB are driven by the 32 outputs from the PTSA or the PTSA bypass. Each

macrocell contains a programmable XOR gate, a programmable register/latch ﬂip-ﬂop and the necessary clocks

and control logic to allow combinatorial or registered operation.

The macrocells each have two outputs, which can be fed to the GRP and I/O cell. This dual or concurrent output

capability from the macrocell gives efﬁcient use of the hardware resources. One output can be a registered function

for example, while the other output can be an unrelated combinatorial function. A direct register input from the I/O

cell facilitates efﬁcient use of the macrocell to construct high-speed input registers.

Macrocell registers can be clocked from one of several global or product term clocks available on the device. A glo-

bal and product term clock enable is also provided, eliminating the need to gate the clock to the macrocell registers

directly. Reset and preset for the macrocell register is provided from both global and product term signals. The

macrocell register can be programmed to operate as a D-type register or a D-type latch. Figure 5 is a graphical rep-

resentation of the ispMACH 5000B macrocell.

Figure 5. ispMACH 5000B Macrocell

From

GRP

PT OE to

I/O Block

From

I/O Cell

PTSA Bypass

Output

to I/O Block

PTSA

PT Clock

Clk En

GRP

R/L

Shared PT Clock

CLK0

CLK1

CLK2

CLK3

Speed/

Power

Clk

PT Preset

PT Reset

Shared PT Reset

Global Reset

AND Array

Dual-OR Array

Macrocell

I/O Cell

The ispMACH 5000B I/O cell provides a high degree of ﬂexibility. It includes the sysIO feature and an enhanced

output enable MUX for optimal performance both on- and off-chip. The sysIO feature allows I/O cells to be conﬁg-

ured to different I/O standards, drive strengths and slew rates. The enhanced output enable MUX provides up to 14

different output enable choices per I/O cell.

The I/O cell contains an output enable (OE) MUX, a programmable tri-state output buffer, a programmable input

buffer, a programmable pull-up resistor, a programmable pull-down resistor and a programmable bus-friendly latch.

The I/O cell receives its input from its associated macrocell. The I/O cell has a feedback line to its associated mac-

rocell and a direct path to the GRP.

The output enable (OE) MUX selects the OE signal per I/O cell. The inputs to the OE MUX are the four shared

PTOE signals, PTOE, the two GOE signals. The OE MUX also has the ability to choose either the true or inverse of

Recommended Resources

Stabilized power supply circuit diagram with current limiting circuit

coin flip game

Transistor characteristic curve grapher circuit

Producing RF modulator circuit for Zhongbao camcorder

HIC1015 protects IC data

TDA1083 power amplifier circuit

Brushless DC Motor (BLDC) Basics: The brushless DC motor (BLDC) is a type of motor that is rapidly gaining popularity and is used in industries such as home appliances, automotive, aerospace, consumer products, medical, and industrial...; 安_然 Analog electronics

Wireless monitoring is the development direction and technological improvement is imperative: Compared with traditional monitoring solutions, wireless monitoring has the following three advantages: 1. Low overall cost, only one-time investment is required, no trenching and pipe laying is requi...; xyh_521 Industrial Control Electronics

Say goodbye to website hacking and virus installation!: Websites are hacked and invaded. I believe this is a headache for many webmasters! Several major IDC hosting providers in China have not found a solution to this problem! Why is my website hacked even...; iceflasher Embedded System

Various bus transmission rates: 1. USB bus USB1.1: -------Low speed mode: 1.5Mbps -------Full speed mode: 12Mbps USB2.0: backward compatible. Added high-speed mode, with a maximum rate of 480Mbps. -------High speed mode: 25~480Mbps ...; Aguilera Microcontroller MCU

CCS5C Language: MSP430 microcontroller is easy to use, CCS5 is useful, but there are few introductory articles on the basics of C language for CCS5!...; 7Sky-xgc Microcontroller MCU

Three issues that should be paid attention to when making an amplifier: [backcolor=white]Making an amplifier is actually a highly technical job, and the following three things should be considered and paid attention to. 1. Selection of the scheme First determine the vario...; 莫妮卡 Analogue and Mixed Signal

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components