STK11C88-3
32K x 8 nvSRAM
3.3V
QuantumTrap™
CMOS
Nonvolatile Static RAM
ADVANCE
FEATURES
• Operating V
CC
Range: 3.0V-3.6V
• 45ns and 55ns Access Times
•
STORE
to EEPROM Initiated by Software
•
RECALL
to SRAM Initiated by Software or
Power Restore
• 8mA Typical I
CC
at 200ns Cycle Time
• Unlimited READ, WRITE and
RECALL
Cycles
• 1,000,000
STORE
Cycles to EEPROM
• 100-Year Data Retention in EEPROM
• Commercial and Industrial Temperatures
• 28-Pin DIP and SOIC Packages
DESCRIPTION
The Simtek STK11C88-3 is a fast static
RAM
with a
nonvolatile, electrically erasable
PROM
element
incorporated in each static memory cell. The
SRAM
can be read and written an unlimited number of
times, while independent nonvolatile data resides in
EEPROM
. Data transfers from the
SRAM
to the
EEPROM
(the
STORE
operation), or from
EEPROM
to
SRAM
(the
RECALL
operation) take place using a
software sequence. Transfers from the
EEPROM
to
the
SRAM
(the
RECALL
operation) also take place
automatically on restoration of power.
BLOCK DIAGRAM
EEPROM ARRAY
512 x 512
PIN CONFIGURATIONS
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
5
A
6
A
7
A
8
A
9
A
11
A
12
A
13
A
14
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
STORE
STATIC RAM
ARRAY
512 x 512
RECALL
STORE/
RECALL
CONTROL
SOFTWARE
DETECT
INPUT BUFFERS
COLUMN I/O
COLUMN DEC
A
0
- A
13
V
CC
W
A
13
A
8
A
9
A
11
G
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
ROW DECODER
28 - 300 PDIP
28 - 600 PDIP
28 - 300 SOIC
28 - 350 SOIC
PIN NAMES
A
0
- A
14
W
Address Inputs
Write Enable
Data In/Out
Chip Enable
Output Enable
Power (+ 3.3V)
Ground
A
0
A
1
A
2
A
3
A
4
A
10
DQ
0
- DQ
7
G
E
W
E
G
V
CC
V
SS
July 1999
5-11
STK11C88-3
ABSOLUTE MAXIMUM RATINGS
a
Voltage on Input Relative to V
SS
. . . . . . . . . . –0.6V to (V
CC
+ 0.5V)
Voltage on DQ
0-7
. . . . . . . . . . . . . . . . . . . . . . –0.5V to (V
CC
+ 0.5V)
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . . 15mA
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at condi-
tions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
DC CHARACTERISTICS
COMMERCIAL
SYMBOL
I
CC
I
CC
I
CC
I
SB
I
SB
b
1
c
2
b
3
d
(V
CC
= 3.0V-3.6V)
INDUSTRIAL
UNITS
MIN
MAX
35
30
3
8
9
8
1
±1
±5
2.2
V
SS
– .5
2.4
0.4
0
70
–40
V
CC
+ .5
0.8
2.2
V
SS
– .5
2.4
0.4
85
MIN
MAX
37
32
3
8
10
9
1
±1
±5
V
CC
+ .5
0.8
mA
mA
mA
mA
mA
mA
mA
µA
µA
V
V
V
V
°C
t
AVAV
= 45ns
t
AVAV
= 55ns
All Inputs Don’t Care, V
CC
= max
W
≥
(V
CC
– 0.2V)
All Others Cycling, CMOS Levels
t
AVAV
= 45ns, E
≥
V
IH
t
AVAV
= 55ns, E
≥
V
IH
E
≥
(V
CC
- 0.2V)
All Others V
IN
≤
0.2V or
≥
(V
CC
– 0.2V)
V
CC
= max
V
IN
= V
SS
to V
CC
V
CC
= max
V
IN
= V
SS
to V
CC
, E or G
≥
V
IH
All Inputs
All Inputs
I
OUT
= – 1mA
I
OUT
= 2mA
NOTES
PARAMETER
Average V
CC
Current
Average V
CC
Current During
STORE
Average V
CC
Current at t
AVAV
= 200ns
3.3V, 25°C, Typical
Average V
CC
Current
(Standby, Cycling TTL Input Levels)
V
CC
Standby Current
(Standby, Stable CMOS Input Levels)
Input Leakage Current
Off-State Output Leakage Current
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
Operating Temperature
1
d
2
I
ILK
I
OLK
V
IH
V
IL
V
OH
V
OL
T
A
Note b: I
CC
and I
CC
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
1
3
Note c: I
CC
is the average current required for the duration of the
STORE
cycle (t
STORE
) .
Note d: E
≥
2
V
IH
will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 3.0V
Input Rise and Fall Times
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤
5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
3.0V
1.1KOhms
OUTPUT
1.55KOhms
CAPACITANCE
e
SYMBOL
C
IN
C
OUT
PARAMETER
Input Capacitance
Output Capacitance
(T
A
= 25°C, f = 1.0MHz)
MAX
5
7
UNITS
pF
pF
CONDITIONS
∆V
= 0 to 3V
∆V
= 0 to 3V
30 pF
INCLUDING
SCOPE AND
FIXTURE
Note e: These parameters are guaranteed but not tested.
Figure 1: AC Output Loading
July 1999
5-12
STK11C88-3
SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
1
2
3
4
5
6
7
8
9
10
11
PARAMETER
#1, #2
t
ELQV
t
AVAVf
t
AVQVg
t
GLQV
t
AXQXg
t
ELQX
t
EHQZh
t
GLQX
t
GHQZh
t
ELICCHe
t
EHICCLd, e
Alt.
t
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
t
OHZ
t
PA
t
PS
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
0
45
0
15
0
55
5
5
15
0
20
45
45
20
3
5
20
MIN
MAX
45
55
55
25
MIN
MAX
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(V
CC
= 3.0V-3.6V)
STK11C88-3-45
STK11C88-3-55
UNITS
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note g: I/O state assumes E and G < V
IL
and W > V
IH
; device is continuously selected.
Note h: Measured
±
200mV from steady state output voltage.
SRAM READ CYCLE #1:
Address Controlled
f, g
t
AVAV
ADDRESS
5
t
AXQX
3
2
t
AVQV
DATA VALID
DQ (DATA OUT)
SRAM READ CYCLE #2:
E Controlled
f
t
AVAV
ADDRESS
t
ELQV
E
t
ELQX
t
EHQZ
7
6
1
2
t
EHICCL
1
1
G
4
t
GLQV
t
GHQZ
9
t
GLQX
DQ (DATA
t
ELICCH
I
CC
STANDBY
10
ACTIVE
DATA VALID
8
July 1999
5-13
STK11C88-3
SRAM WRITE CYCLES #1 & #2
SYMBOLS
NO.
#1
12
13
14
15
16
17
18
19
20
21
t
AVAV
t
WLWH
t
ELWH
t
DVWH
t
WHDX
t
AVWH
t
AVWL
t
WHAX
t
WLQZh, i
t
WHQX
#2
t
AVAV
t
WLEH
t
ELEH
t
DVEH
t
EHDX
t
AVEH
t
AVEL
t
EHAX
Alt.
t
WC
t
WP
t
CW
t
DW
t
DH
t
AW
t
AS
t
WR
t
WZ
t
OW
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
5
PARAMETER
MIN
45
30
30
15
0
30
0
0
15
5
MAX
MIN
55
40
40
25
0
40
0
0
20
MAX
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(V
CC
= 3.0V-3.6V)
STK11C88-3-45 STK11C88-3-55
UNITS
Note i:
Note j:
If W is low when E goes low, the outputs remain in the high-impedance state.
E or W must be
≥
V
IH
during address transitions.
SRAM WRITE CYCLE #1:
W Controlled
j
t
AVAV
ADDRESS
t
ELWH
E
14
19
12
t
WHAX
t
AVWH
t
AVWL
W
t
WLWH
15
16
13
18
17
t
DVWH
DATA IN
t
WLQZ
DATA OUT
PREVIOUS DATA
HIGH IMPEDANCE
20
DATA VALID
t
WHDX
t
WHQX
21
SRAM WRITE CYCLE #2:
E Controlled
j
t
AVAV
ADDRESS
t
AVEL
E
18
14
19
12
t
ELEH
t
EHAX
t
AVEH
t
WLEH
W
t
DVEH
DATA IN
DATA OUT
HIGH IMPEDANCE
DATA VALID
15
13
17
t
EHDX
16
July 1999
5-14
STK11C88-3
STORE
INHIBIT/POWER-UP
RECALL
SYMBOLS
NO.
Standard
22
23
24
25
t
RESTORE
t
STORE
V
SWITCH
V
RESET
Power-up
RECALL
Duration
STORE
Cycle Duration
Low Voltage Trigger Level
Low Voltage Reset Level
2.7
PARAMETER
MIN
MAX
550
10
3.0
2.6
µs
ms
V
V
k
(V
CC
= 3.0V-3.6V)
STK11C88-3
UNITS
NOTES
Note k: t
RESTORE
starts from the time V
CC
rises above V
SWITCH
.
STORE
INHIBIT/POWER-UP
RECALL
V
CC
3.3V
24
V
SWITCH
25
V
RESET
STORE
INHIBIT
OWER-UP
RECALL
22
t
RESTORE
DQ (DATA OUT)
POWER-UP
RECALL
BROWN OUT
STORE
INHIBIT
NO
RECALL
(V
CC
DID NOT GO
BELOW V
RESET
)
BROWN OUT
STORE
INHIBIT
NO
RECALL
(V
CC
DID NOT GO
BELOW V
RESET
)
BROWN OUT
STORE
INHIBIT
RECALL
WHEN
V
CC
RETURNS
ABOVE V
SWITCH
July 1999
5-15
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