®
RT3667BL
Dual-Output PWM Controller with 2 Integrated Drivers for
AMD SVI2 CPU Power Supply
General Description
The RT3667BL is a 4 + 2 phases PWM controller, and is
compliant with AMD SVI2 Voltage Regulator Specification
to support both CPU core (VDD) and Northbridge portion
of the CPU (VDDNB). The RT3667BL features CCRCOT
(Constant Current Ripple Constant On-Time) with the G-
NAVP (Green-Native AVP), which is Richtek's proprietary
topology. The G-NAVP makes it an easy setting controller
to meet all AMD AVP (Active Voltage Positioning) VDD/
VDDNB requirements. The droop is easily programmed
by setting the DC gain of the error amplifier. With proper
compensation, the load transient response can achieve
optimized AVP performance. The controller also uses the
interface to issue VOTF Complete and to send digitally
encoded voltage and current values for the VDD and
VDDNB domains. It can operate in single phase and diode
emulation mode and reach up to 90% efficiency in different
modes according to different loading conditions. The
RT3667BL provides special purpose offset capabilities by
pin setting. The RT3667BL also provides power good
indication, over-current indication (OCP_L) and dual OCP
mechanism for AMD SVI2 CPU core and NB. It also
features fault protection functions, including over-voltage,
under-voltage and negative voltage protections.
Features
4/3/2/1-Phase (VDD) + 2/1/0-Phase (VDDNB) PWM
Controller
2 Embedded MOSFET Drivers at the VDD Controller
G-NAVP
TM
Topology
Support Dynamic Load-Line and Zero Load-Line
Diode Emulation Mode at Light Load Condition
SVI2 Interface to Comply AMD Power Management
Protocol
Build-In ADC for V
OUT
and I
OUT
Reporting
Immediate OV, UV and NV Protections and UVLO
Programmable Dual OCP Mechanism
0.5% DAC Accuracy
Fast Transient Response
Power Good Indicator
Over-Current Indicator
52-Lead WQFN Package
Applications
AMD SVI2 CPU
Desktop Computer
Simplified Application Circuit
RT3667BL
OCP_L
PHASE1
PHASE2
SVC
To CPU
SVD
SVT
PWM3
PWM4
PWMA1
PWMA2
MOSFET
MOSFET
RT9624A
RT9624A
RT9624A
RT9624A
MOSFET
MOSFET
MOSFET
MOSFET
V
VDDNB
V
VDD
Copyright
©
2019 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
DS3667BL-00
September
2019
www.richtek.com
RT3667BL
Ordering Information
RT3667BL
Package Type
QW : WQFN-52L 6x6 (W-Type)
Lead Plating System
G : Green (Halogen Free and Pb Free)
Note :
Richtek products are :
½
Pin Configuration
(TOP VIEW)
PWM3
BOOT2
UGATE2
PHASE2
LGATE2
PVCC
LGATE1
PHASE1
UGATE1
BOOT1
PWMA1
PWMA2
TONSETA
52 51 50 49 48 47 46 45 44 43 42 41 40
RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
Suitable for use in SnPb or Pb-free soldering processes.
½
Marking Information
RT3667BLGQW : Product Number
Functional Pin Description
Pin No.
1, 52
2
5, 4, 8, 9
6, 3, 7, 10
11
12
13
14
15
Pin Name
PWM4, PWM3
TONSET
ISEN1N to ISEN4N
ISEN1P to ISEN4P
VSEN
FB
COMP
RGND
IMON
Pin Function
PWM outputs for Channel 3 and 4 of VDD controller.
VDD controller on-time setting. Connect this pin to the converter input
voltage, VIN, through a resistor, RTON, to set the on-time of UGATE and
also the output voltage ripple of VDD controller.
Negative current sense input of Channel 1, 2, 3 and 4 for VDD controller.
Positive current sense input of Channel 1, 2, 3 and 4 for VDD controller.
VDD controller voltage sense input. This pin is connected to the terminal
of VDD controller output voltage.
Output voltage feedback input of VDD controller. This pin is the negative
input of the error amplifier for the VDD controller.
Compensation node of the VDD controller.
Return ground of VDD and VDDNB controller. This pin is the common
negative input of output voltage differential remote sense for VDD and
VDDNB controllers.
Current monitor output for the VDD controller. This pin outputs a voltage
proportional to the output current.
This pin provides two functions: Fixed 0.64V Reference Voltage Output
and Current Gain Ratio Setting for VDD and VDDNB Controller. Connect a
resistive voltage divider from VCC to GND and connect the joint of the
voltage divider to this pin for current gain ration setting. The pin also used
to offset the output voltage of the IMON pin and the IMONA pin. Bypass
this pin to GND with the 22nF ceramic capacitor for noise decoupling and
pin setting accuracy.
is a registered trademark of Richtek Technology Corporation.
16
V064/SET3
Copyright
©
2019 Richtek Technology Corporation. All rights reserved.
www.richtek.com
2
RGND
IMON
V064/SET3
IMONA
VDDIO
PWROK
SVC
SVD
SVT
OFS
OFSA
SET1
SET2
RT3667BL
GQW
YMDNN
YMDNN : Date Code
PWM4
TONSET
ISEN2P
ISEN2N
ISEN1N
ISEN1P
ISEN3P
ISEN3N
ISEN4N
ISEN4P
VSEN
FB
COMP
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19 20 21 22 23 24 25 26
53
39
38
37
36
35
34
GND
33
32
31
30
29
28
27
PGOOD
PGOODA
EN
ISENA1P
ISENA1N
ISENA2N
ISENA2P
VSENA
FBA
COMPA
IBIAS
VCC
OCP_L
WQFN-52L 6x6
DS3667BL-00
September
2019
RT3667BL
Pin No.
17
18
Pin Name
IMONA
VDDIO
Pin Function
Current monitor output for the VDDNB controller. This pin outputs a
voltage proportional to the output current.
Processor memory interface power rail and serves as the reference for
PWROK, SVD, SVC and SVT. This pin is used by the VR to reference the
SVI pins.
System power good input. If PWROK is low, the SVI interface is disabled
and VR returns to BOOT-VID state with initial load line slope and initial
offset. If PWROK is high, the SVI interface is running and the DAC
decodes the received serial VID codes to determine the output voltage.
Serial VID clock input from processor.
Serial VID data input from processor. This pin is a serial data line.
Serial VID telemetry input from VR. This pin is a push-pull output.
Over clocking offset setting for the VDD controller.
Over clocking special purpose offset setting for the VDDNB controller.
1st platform setting. Platform can use this pin to set OCP_TDC threshold,
DVID compensation bit1 and internal ramp slew rate.
2st platform setting. Platform can use this pin to set quick response
threshold, OCP_TDC trigger delay time, DVID compensation bit0 and
over clocking offset enable setting.
Over current indicator for dual OCP mechanism. This pin is an open drain
output.
Controller power supply input. Connect this pin to 5V with an 1F or
greater ceramic capacitor for decoupling.
Internal bias current setting. Connect only a 100k resistor from this pin
to GND to generate bias current for internal circuit. Place this resistor as
close to IBIAS pin as possible.
Compensation node of the VDDNB controller.
Output voltage feedback input of VDDNB controller. This pin is the
negative input of the error amplifier for the VDDNB controller.
VDDNB controller voltage sense input. This pin is connected to the
terminal of VDDNB controller output voltage.
Positive current sense input of Channel 1 and 2 for VDDNB controller.
Negative current sense input of Channel 1 and 2 for VDDNB controller.
Controller enable control input. A logic high signal enables the controller.
Power good indicator for the VDDNB controller. This pin is an open*drain
output.
Power good indicator for the VDD controller. This pin is an open-drain
output.
VDDNB controller on-time setting. Connect this pin to the converter input
voltage, VIN, through a resistor, RTONNB, to set the on-time of
UGATE_VDDNB and also the output voltage ripple of VDDNB controller.
PWM output for Channel 1 and 2 of VDDNB controller.
Bootstrap supply for high-side MOSFET. This pin powers high-side
MOSFET driver.
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33, 36
34, 35
37
38
39
40
41, 42
43, 51
PWROK
SVC
SVD
SVT
OFS
OFSA
SET1
SET2
OCP_L
VCC
IBIAS
COMPA
FBA
VSENA
ISENA2P, ISENA1P
ISENA2N, ISENA1N
EN
PGOODA
PGOOD
TONSETA
PWMA2, PWMA1
BOOT1, BOOT2
Copyright
©
2019 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
DS3667BL-00
September
2019
www.richtek.com
3
RT3667BL
Pin No.
44, 50
45, 49
46, 48
47
53
(Exposed Pad)
Pin Name
UGATE1, UGATE2
PHASE1, PHASE2
LGATE1, LGATE2
PVCC
GND
Pin Function
High-side gate driver outputs. Connect this pin to Gate of high-side
MOSFET.
Switch nodes of high-side driver. Connect this pin to high-side MOSFET
Source together with the low-side MOSFET Drain and the inductor.
Low-side gate driver outputs. This pin drives the Gate of low-side
MOSFET.
Driver power. Connect this pin to GND by ceramic capacitor larger than
1F.
Ground. The exposed pad must be soldered to a large PCB and
connected to GND for maximum power dissipation.
SVC
IMONI
IMONAI
SET3
MUX
ADC
IBIAS
From Control Logic
RGND
DAC
VSETA
ERROR
AMP
+
-
FBA
COMPA
ISENA1P
ISENA1N
+
x2
-
Offset
Cancellation
SVI2 Interface
Configuration Registers
Control Logic
OFS/OFSA
Load Line
/Load Line A
RSET/RSETA
OCP Threshold
+
POR
UVLO
PGOODA
PWROK
PGOOD
Functional Block Diagram
VSEN
VSENA
VDDIO
OFSA
SET1
SET2
OFS
SVD
SVT
OCP_L
PVCC
VCC
EN
GND
Loop Control
Protection Logic
TONSETA
PWM
CMPA
QRA
TONA
PWMA1
TON
GENA
PWMA2
Soft-Start & Slew
Rate Control
+
0.4*A
i_VDDNB
+
V064
-
RSETA
Average
IMONAI
-
Current mirror
IBA1
Current mirror
ISENA2P
ISENA2N
IMONA
From Control Logic
RGND
DAC
Soft-Start & Slew Rate
Control
Current Balance
IBA1
IBA2
+
x2
-
IBA2
OCP_TDCA,
OCP_SPIKEA
+
-
OCA
To Protection Logic
OV/UV/NV
PWM
CMP
QR
TON
TON
GEN
PWM1
PWM2
2-PH
Driver
TONSET
BOOTx
UGATEx
PHASEx
LGATEx
PWM3
PWM4
VSENA
ERROR
AMP
+
-
Current mirror
VSET
FB
COMP
ISEN1P
ISEN1N
+
x1
-
IB1
Offset
Cancellation
+
+
0.4*A
i_VDD
+
-
RSET
V064
Average
IMONI
-
Current mirror
ISEN2P
ISEN2N
+
x1
-
IB2
Current mirror
ISEN3P
ISEN3N
+
x1
-
IB3
Current mirror
ISEN4P
ISEN4N
+
x1
-
IB4
Current Balance
IB1
IB2
IB3
IB4
OCP_TDC,
OCP_SPIKE
SET3
+
-
OC
VSEN
To Protection Logic
OV/UV/NV
IMON V064/SET3
Copyright
©
2019 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
4
DS3667BL-00
September
2019
RT3667BL
Operation
MUX and ADC
The MUX supports the inputs from SET1, SET2, SET3,
OFS, OFSA, IMON, IMONA, VSEN, or VSENA. The ADC
converts these analog signals to digital codes for reporting
or performance adjustment.
SVI2 Interface
The SVI2 interface uses the SVC, SVD, and SVT pins to
communicate with CPU. The RT3667BL's performance and
behavior can be adjusted by commands sent by CPU or
platform.
UVLO
The UVLO detects the VCC pin voltages for under-voltage
lockout protection and power on reset operation.
Loop Control Protection Logic
Loop control protection logic detects EN and UVLO signals
to initiate soft-start function and control PGOOD,
PGOODA and OCP_L signals after soft-start is finished.
When dual OCP event occurs, the OCP_L pin voltage will
be pulled low.
DAC
The DAC receives VID codes from the SVI2 control logic
to generate an internal reference voltage (VSET/VSETA)
for controller.
Soft-Start and Slew-Rate Control
This block controls the slew rate of the internal reference
voltage when output voltage changes.
PWM CMPx
The PWM comparator compares COMP signal and current
feedback signal to generate a signal for TONGENx.
TONGEN/TONGENA
This block generates an on-time pulse which high interval
is based on the on-time setting and current balance.
Current Balance
Per-phase current is sensed and adjusted by adjusting
on-time of each phase to achieve current balance for each
phase.
OC/OV/UV/NV
VSEN/VSENA and output current are sensed for over-
current, over-voltage, under-voltage, and negative voltage
protection.
RSET/RSETA
The Ramp generator is designed to improve noise immunity
and reduce jitter.
Error Amp
Error amplifier generates COMP/COMPA signal by the
difference between VSET/VSETA and FB/FBA.
Offset cancellation
This block cancels the output offset voltage from voltage
ripple and current ripple to achieve accurate output voltage.
Copyright
©
2019 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
DS3667BL-00
September
2019
www.richtek.com
5
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