STK10C68
ABSOLUTE MAXIMUM RATINGS
a
Voltage on Input Relative to Ground . . . . . . . . . . . . . .–0.5V to 7.0V
Voltage on Input Relative to V
SS
. . . . . . . . . . –0.6V to (V
CC
+ 0.5V)
Voltage on DQ
0-7
. . . . . . . . . . . . . . . . . . . . . . –0.5V to (V
CC
+ 0.5V)
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . . 15mA
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at condi-
tions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
DC CHARACTERISTICS
SYMBOL
I
CC
b
1
(V
CC
= 5.0V
±
10%)
COMMERCIAL
MIN
MAX
85
75
65
N/A
3
10
27
23
20
N/A
750
±1
±5
2.2
V
SS
– .5
2.4
0.4
0
70
–40/-55
V
CC
+ .5
0.8
2.2
V
SS
– .5
2.4
0.4
85/125
INDUSTRIAL/
MILITARY
MIN
MAX
90
75
65
55
3
10
28
24
21
20
1500
±1
±5
V
CC
+ .5
0.8
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
µA
V
V
V
V
°C
t
AVAV
= 25ns
t
AVAV
= 35ns
t
AVAV
= 45ns
t
AVAV
= 55ns
All Inputs Don’t Care, V
CC
= max
W
≥
(V
CC
– 0.2V)
All Others Cycling, CMOS Levels
t
AVAV
= 25ns, E
≥
V
IH
t
AVAV
= 35ns, E
≥
V
IH
t
AVAV
= 45ns, E
≥
V
IH
t
AVAV
= 55ns, E
≥
V
IH
E
≥
(V
CC
– 0.2V)
All Others V
IN
≤
0.2V or
≥
(V
CC
– 0.2V)
V
CC
= max
V
IN
= V
SS
to V
CC
V
CC
= max
V
IN
= V
SS
to V
CC
, E or G
≥
V
IH
All Inputs
All Inputs
I
OUT
= – 4mA
I
OUT
= 8mA
UNITS
NOTES
PARAMETER
Average V
CC
Current
I
CC
c
2
3
Average V
CC
Current during
STORE
Average V
CC
Current at t
AVAV
= 200ns
5V, 25°C, Typical
Average V
CC
Current
(Standby, Cycling TTL Input Levels)
I
CC
b
I
SB
d
1
I
SB
d
2
V
CC
Standby Current
(Standby, Stable CMOS Input Levels)
Input Leakage Current
Off-State Output Leakage Current
Input Logic “1” Voltage
Input Logic “0” Voltage
I
ILK
I
OLK
V
IH
V
IL
V
OH
V
OL
T
A
Note a: Output Logic “1” Voltage
Output Logic “0” Voltage
Operating Temperature
Note b: I
CC
and I
CC
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
1
3
Note c: I
CC
is the average current required for the duration of the
STORE
cycle (t
STORE
) .
2
Note d: E
≥
V
IH
will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤
5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
5.0V
480 Ohms
OUTPUT
255 Ohms
CAPACITANCE
e
SYMBOL
C
IN
C
OUT
PARAMETER
Input Capacitance
Output Capacitance
(T
A
= 25
°
C, f = 1.0MHz)
MAX
8
7
UNITS
pF
pF
CONDITIONS
∆V
= 0 to 3V
∆V
= 0 to 3V
30 pF
INCLUDING
SCOPE AND
FIXTURE
Note e: These parameters are guaranteed but not tested.
Figure 1: AC Output Loading
September 2003
2
Document Control # ML0006 rev 0.1
STK10C68
SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
1
2
3
4
5
6
7
8
9
10
11
#1, #2
t
ELQV
t
AVAV
f
g
(V
CC
= 5.0V
±
10%)
STK10C68-25
MIN
MAX
25
25
25
10
5
5
10
0
10
0
25
0
35
0
10
0
45
5
5
10
0
12
0
55
35
35
15
5
5
12
0
12
STK10C68-35
MIN
MAX
35
45
45
20
5
5
12
STK10C68-45
MIN
MAX
45
55
55
25
STK10C68-55
MIN
MAX
55
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Alt.
t
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
PARAMETER
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
t
AVQV
t
GLQV
t
AXQX
t
ELQX
t
EHQZ
h
t
GLQX
t
GHQZ
h
e
d, e
g
t
OHZ
t
PA
t
PS
t
ELICCH
t
EHICCL
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles. NE must be high during entire cycle.
Note g: I/O state assumes E, G < V
IL
, W > V
IH
, and NE
≥
V
IH
; device is continuously selected.
Note h: Measured + 200mV from steady state output voltage.
SRAM READ CYCLE #1:
Address Controlled
f, g
t
AVAV
ADDRESS
t
AXQX
DQ (DATA OUT)
5
3
2
t
AVQV
DATA VALID
SRAM READ CYCLE #2:
E Controlled
f
t
AVAV
ADDRESS
t
ELQV
E
6
t
ELQX
1
1
1
2
t
EHICCL
7
t
EHQZ
G
8
t
GLQV
4
t
GHQZ
9
t
GLQX
DQ (DATA OUT)
10
t
ELICCH
ACTIVE
DATA VALID
I
CC
STANDBY
September 2003
3
Document Control # ML0006 rev 0.1
STK10C68
SRAM WRITE CYCLES #1 & #2
NO.
12
13
14
15
16
17
18
19
20
21
SYMBOLS
#1
t
AVAV
t
WLWH
t
ELWH
t
DVWH
t
WHDX
t
AVWH
t
AVWL
t
WHAX
t
WLQZ
h, i
t
WHQX
#2
t
AVAV
t
WLEH
t
ELEH
t
DVEH
t
EHDX
t
AVEH
t
AVEL
t
EHAX
Alt.
t
WC
t
WP
t
CW
t
DW
t
DH
t
AW
t
AS
t
WR
t
WZ
t
OW
PARAMETER
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
5
STK10C68-25
MIN
25
20
20
10
0
20
0
0
10
5
MAX
STK10C68-35
MIN
35
25
25
12
0
25
0
0
13
5
MAX
MIN
45
30
30
15
0
30
0
0
14
5
(V
CC
= 5.0V
±
10%)
STK10C68-45
MAX
STK10C68-55
MIN
55
45
45
30
0
45
0
0
15
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note i:
Note j:
If W is low when E goes low, the outputs remain in the high-impedance state.
E or W must be
≥
V
IH
during address transitions. NE
≥
V
IH
.
SRAM WRITE CYCLE #1:
W Controlled
j
t
AVAV
ADDRESS
t
ELWH
E
14
19
12
t
WHAX
t
AVWL
W
18
t
AVWH
t
WLWH
15
13
17
t
DVWH
DATA IN
t
WLQZ
DATA OUT
PREVIOUS DATA
HIGH IMPEDANCE
20
DATA VALID
16
t
WHDX
t
WHQX
21
SRAM WRITE CYCLE #2:
E Controlled
j
t
AVAV
ADDRESS
t
AVEL
E
18
14
19
12
t
ELEH
t
EHAX
t
AVEH
W
t
WLEH
15
16
13
17
t
DVEH
DATA IN
DATA OUT
HIGH IMPEDANCE
DATA VALID
t
EHDX
September 2003
4
Document Control # ML0006 rev 0.1
FPGA/CPLD
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