5962R-0626105QXX datasheet, PDF

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5962R-0626105QXX: DescriptionStandard SRAM, 512KX32, 20ns, CMOS, CQFP68, CERAMIC, QFP-68; Categorystorage storage; File Size405KB，20 Pages; ManufacturerCobham Semiconductor Solutions

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5962R-0626105QXX Overview

Standard SRAM, 512KX32, 20ns, CMOS, CQFP68, CERAMIC, QFP-68

5962R-0626105QXX Parametric

Parameter Name	Attribute value
Maker	Cobham Semiconductor Solutions
Parts packaging code	QFP
package instruction	GQFF,
Contacts	68
Reach Compliance Code	unknow
ECCN code	3A001.A.2.C
Maximum access time	20 ns
JESD-30 code	S-CQFP-F68
length	24.892 mm
memory density	16777216 bi
Memory IC Type	STANDARD SRAM
memory width	32
Number of functions	1
Number of terminals	68
word count	524288 words
character code	512000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	512KX32
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	GQFF
Package shape	SQUARE
Package form	FLATPACK, GUARD RING
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Filter level	MIL-PRF-38535 Class Q
Maximum seat height	3.302 mm
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	FLAT
Terminal pitch	1.27 mm
Terminal location	QUAD
total dose	100k Rad(Si) V
width	24.892 mm

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Standard Products

Data Sheet

UT8ER512K32 Monolithic 16M SRAM

January 31, 2011

www.aeroflex.com/memories

FEATURES

20ns Read, 10ns Write maximum access times

Functionally compatible with traditional 512K x 32 SRAM

devices

CMOS compatible input and output levels, three-state

bidirectional data bus

- I/O Voltage 3.3 volt, 1.8 volt core

Operational environment:

- Total-dose: 100 krad(Si)

- SEL Immune: 111MeV-cm

/mg

- SEU error rate = 6.0x10

-16

errors/bit-day assuming

geosynchronous orbit, Adam’s 90% worst environment,

and 6600ns default Scrub Rate Period (=97% SRAM

availability)

Packaging options:

- 68-lead ceramic quad flatpack (6.898 grams)

Standard Microcircuit Drawing 5962-06261

- QML Q & V

INTRODUCTION

The UT8ER512K32 is a high-performance CMOS static RAM

organized as 524,288 words by 32 bits. Easy memory expansion

is provided by active LOW and HIGH chip enables (E1, E2), an

active LOW output enable (G), and three-state drivers. This

device has a power-down feature that reduces power

consumption by more than 90% when deselected.

Writing to the device is accomplished by driving chip enable one

(E1) input LOW, chip enable two (E2) HIGH and write enable

(W) input LOW. Data on the 32 I/O pins (DQ0 through DQ31)

is then written into the location specified on the address pins (A0

through A18). Reading from the device is accomplished by

taking chip enable one (E1) and output enable (G) LOW while

forcing write enable (W) and chip enable two (E2) HIGH. Under

these conditions, the contents of the memory location specified

by the address pins will appear on the I/O pins.

The 32 input/output pins (DQ0 through DQ31) are placed in a

high impedance state when the device is deselected (E1 HIGH

or E2 LOW), the outputs are disabled (G HIGH), or during a

write operation (E1 LOW, E2 HIGH and W LOW).

Row Select

A17

A18

Column Select

Memory Array

512K x 32

Pre-Charge Circuit

I/O Circuit

DQ(31) to DQ(0)

Read/Write

Circuit

Data Control

A10 A11 A12 A13 A14 A15 A16

EDAC

BUSY, SCRUB

MBE

Figure 1. UT8ER512K32 SRAM Block Diagram

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