Clock OSC
SG7050EBN
SG7050EBN 125.000000MHz CJGA
Product name
X1G0045110002xx
Product Number / Ordering code
Please refer to the 9.Packing information about xx (last 2 digits)
Output waveform
LV-PECL
Pb free / Complies with EU RoHS directive
Reference weight Typ. 171 mg
1.Absolute maximum ratings
Parameter
Symbol
Maximum supply voltage
Storage temperature
Input voltage
Min.
-0.3
-55
-0.3
Typ.
-
-
-
Max.
+4
+125
Vcc+0.3
Unit
V
ºC
V
Conditions / Remarks
-
Storage as single product
ST or OE Terminal
Vcc-GND
T_stg
Vin
2.Specifications(characteristics)
Parameter
Symbol
Output frequency
Supply voltage
Operating temperature
Frequency tolerance
Current consumption
Stand-by current
Disable current
Symmetry
Output voltage(LV-PECL)
Output load condition(ECL)
Input voltage
Rise time
Fall time
Start-up time
Jitter
Min.
Typ.
Max.
3.465
+85
50
75
-
0.0
55
-
Vcc-1.62
-
-
30% Vcc
0.4
0.4
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Unit
MHz
V
ºC
x10
-6
mA
mA
mA
%
V
V
Ω
Conditions / Remarks
-
-
-
OE = Vcc , L_ECL = 50 ohm
-
OE=GND
At output crossing point
-
-
Terminated to Vcc - 2.0V
OE Terminal
OE Terminal
Phase jitter
Phase noise
f0
Vcc
T_use
f_tol
Icc
I_std
I_dis
SYM
V
OH
V
OL
L_ECL
V
IH
V
IL
t
r
tf
t_str
t
DJ
T
RJ
t
RMS
t
p-p
t
acc
t
PJ
L(f)
Frequency aging
f_age
125.0000
3.135
3.3
-40
-
-50
-
-
-
-
-
-
-
45
-
Vcc-1.025
-
-
-
-
50
70% Vcc
-
-
-
-
-
-
-
-
-
-
0.1
-
2.5
-
2.5
-
20
-
3
-
0.08
-
-
-
-68
-
-98
-
-127
-
-142
-
-152
-
-156
-
-
ps
ps
ms
ps
ps
ps
ps
ps
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
At 20% to 80% output swing
At 20% to 80% output swing
-
Deterministic Jitter
Random Jitter
δ(RMS of total distribution)
Peak to Peak
Accumulated Jitter(δ) n=2 to 50000 cycles
Off set Frequency: 12kHz to 20MHz
Off set 1Hz
Off set 10Hz
Off set 100Hz
Off set 1kHz
Off set 10kHz
Off set 100kHz
Off set 1MHz
x10
-6
/Year
Included in Frequency tolerance 10 years
1 Page
3.Test circuit
1) To observe waveform and current (case 1)
Vcc
+3.3 V
________
A
By-pass
capacitor 2
Power
supply 2
Vcc
OUT
OUT
130 Ω
130 Ω
Test Point
OE
OE pin
NC
GND
82 Ω
By-pass
capacitor 1
Test Point
82 Ω
________
* The lines from OUT and OUT pin are same length.
* To measure the disable current, OE pin is connected to GND
2) To observe waveform and current (case 2)
A
+3.3 V
________
Test Point
OUT
OUT
50 Ω
Test Point
50 Ω
Vcc-2 V
By-pass
capacitor 2
Power
supply 2
Vcc
OE
OE pin
NC
GND
By-pass
capacitor 1
________
* The lines from OUT and OUT pin are same length.
* To measure the disable current, OE pin is connected to GND
3) Measurement condition
A) Oscilloscope
•Bandwidth should be 5 times higher than DUT’s output frequency (4 GHz).
•Probe ground should be placed closely from test point and lead length should be as short as possible.
B) By-pass capacitor 1 (approx. 0.01 μF to 0.1 μF) places closely between Vcc and GND.
C) By-pass capacitor 2 (approx. 10 μF) places closely between power supply terminals on the board.
D) Use the current meter whose internal impedance value is small.
E) Power supply
• Start up time (0 Vg90 %Vcc) of power source should be more than 150 μs and
slew rate should be less than 19.8 mV/μs.
• Impedance of power supply should be as low as possible.
2 Page
4.Timing chart
Vcc
80 % of amplitude
tr
tf
________
OUT
20 % of amplitude
Vcc-2 V
OUT
GND
tw
SYM = tw / t
t
5.External dimensions
7.0±0.2
(Unit: mm)
1.4
6.Footprint(Recommended)
1.8
#6
1.1
(Unit: mm)
#6
#5
#4
#5
#4
5.0±0.2
#1
#2
#3
1.4±0.2
5.08
#1
#2
5.08
#3
To maintain stable operation, provide a 0.01uF to 0.1uF
by-pass capacitor at a location as near as possible to the
power source terminal of the crystal product (between Vcc
- GND).
7.Reflow profile
Reflow condition (Follow of JEDEC STD-020D.01)
Temperature[C]
300
250
200
150
100
50
Time
+25CtoPeak
0
60
120 180 240 300 360 420 480 540 600 660 720 780
Time[s]
;+217C
Tsmax;+200C
TL
TP
;+260C
+255C
Avg.
Ramp-up
3
C/sMax.
tp
;20sto40s
tL
60sto150s
(+217Cover)
Ramp-down
6C/sMax.
Tsmin;+150C
ts
60sto180s
(+150Cto+200C)
3 Page
4.2
2.0
8.PCB layout (2 layers, 2nd layer is all GND pattern)
Case 1
* By-pass capacitor (approx. 0.01 μF to 0.1 μF) places closely between Vcc and GND.
* By-pass capacitor (approx. 10 μF) places closely between power supply terminals on the board.
* Please design the two output lines by characteristic impedance 50 Ω and
same length, and try to make the output lines as short as possible.
* Terminators place near the input device.
4 Page
Case 2
* By-pass capacitor (approx. 0.01 μF to 0.1 μF) places closely between Vcc and GND.
* By-pass capacitor (approx. 10 μF) places closely between power supply terminals on the board.
* Please design the two output lines by characteristic impedance 50 Ω and
same length, and try to make the output lines as short as possible.
* Terminators place near the input device.
9.Packing information
[ 1 ]Product number last 2 digits code(xx) description
The recommended code is "00"
Code
13
00
Condition
500pcs / Reel
1000pcs / Reel
X1G0045110002xx
Code
01
11
12
Condition
Any Q'ty vinyl bag(Tape cut)
Any Q'ty / Reel
250pcs / Reel
5 Page
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