Military & Space Products
32K x 8 ROM—SOI
FEATURES
RADIATION
• Fabricated with RICMOS
™
IV Silicon on Insulator
(SOI) 0.75
µm
Process (L
eff
= 0.6
µm)
• Total Dose Hardness through 1x10
6
rad(SiO
2
)
• Typical Operating Power <15 mW/MHz
• Dynamic and Static Transient Upset
Hardness through 1x10
9
rad(Si)/s
• Dose Rate Survivability through 1x10
11
rad(Si)/s
• Neutron Hardness through 1x10
14
cm
-2
• SEU Immune
• Latchup Free
• Asynchronous Operation
• CMOS or TTL Compatible I/O
• Single 5 V
±
10% Power Supply
OTHER
• Read Cycle Times
< 17 ns (Typical)
≤
25 ns (-55 to 125°C)
HX6656
• Packaging Options
- 28-Lead Flat Pack (0.500 in. x 0.720 in.)
- 28-Lead DIP, MIL-STD-1835, CDIP2-T28
- 36-Lead Flat Pack (0.630 in. x 0.650 in.)
GENERAL DESCRIPTION
The 32K x 8 Radiation Hardened ROM is a high perform-
ance 32,768 word x 8-bit read only memory with industry-
standard functionality. It is fabricated with Honeywell’s
radiation hardened technology, and is designed for use in
systems operating in radiation environments. The ROM
operates over the full military temperature range and re-
quires only a single 5 V
±
10% power supply. The ROM is
available with either TTL or CMOS compatible I/O. Power
consumption is typically less than 15 mW/MHz in operation,
and less than 5 mW when de-selected. The ROM operation
is fully asynchronous, with an associated typical access
time of 14 ns.
Honeywell’s enhanced SOI RICMOS
™
IV (Radiation Insen-
sitive CMOS) technology is radiation hardened through the
use of advanced and proprietary design, layout, and pro-
cess hardening techniques. The RICMOS
™
IV process is a
5-volt, SIMOX CMOS technology with a 150 Å gate oxide
and a minimum drawn feature size of 0.75
µm
(0.6
µm
effective gate length—L
eff
). Additional features include
tungsten via plugs, Honeywell’s proprietary SHARP pla-
narization process, and a lightly doped drain (LDD) struc-
ture for improved short channel reliability.
HX6656
FUNCTIONAL DIAGRAM
A:0-8,12-13
11
Row
Decoder
•
•
•
32,768 x 8
Memory
Array
•
•
•
CE
NCS
Column Decoder
Data O utp ut
Q :0-7
8
NO E
CS • CE • OE
(0 = high Z)
Signal
1 = enab led
#
Signal
A:9-11,14
4
All controls must b e
enab led for a signal to
p ass. (#: numb er of
b uffers, default = 1)
SIGNAL DEFINITIONS
A: 0-14
Q: 0-7
NCS
Address input pins which select a particular eight-bit word within the memory array.
Data Output Pins.
Negative chip select, when at a low level allows normal read operation. When at a high level NCS forces the
ROM to a precharge condition, holds the data output drivers in a high impedance state and disables all input
buffers except CE. If this signal is not used it must be connected to VSS.
Negative output enable, when at a high level holds the data output drivers in a high impedance state. When
at a low level, the data output driver state is defined by NCS and CE. If this signal is not used it must be
connected to VSS.
Chip enable, when at a high level allows normal operation. When at a low level CE forces the ROM to a
precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers
except the NCS input buffer. If this signal is not used it must be connected to VDD.
NOE
CE*
TRUTH TABLE
NCS
L
H
X
CE*
H
X
L
NOE
L
XX
XX
MODE
Read
Deselected
Disabled
Q
Data Out
High Z
High Z
Notes:
X: VI=VIH or VIL
XX: VSS≤VI≤VDD
NOE=H: High Z output state maintained
for NCS=X, CE=X
*Not Available in 28-lead DIP or 28-Lead Flat Pack
2
HX6656
RADIATION CHARACTERISTICS
Total Ionizing Radiation Dose
The ROM will meet all stated functional and electrical
specifications over the entire operating temperature range
after the specified total ionizing radiation dose. All electrical
and timing performance parameters will remain within
specifications after rebound at VDD = 5.5 V and T =125°C
extrapolated to ten years of operation. Total dose hardness
is assured by wafer level testing of process monitor transis-
tors and ROM product using 10 keV X-ray and Co60
radiation sources. Transistor gate threshold shift correla-
tions have been made between 10 keV X-rays applied at a
dose rate of 1x10
5
rad(SiO
2
)/min at T = 25°C and gamma
rays (Cobalt 60 source) to ensure that wafer level X-ray
testing is consistent with standard military radiation test
environments.
The ROM will meet any functional or electrical specifica-
tion after exposure to a radiation pulse of
≤50
ns duration
up to 1x10
11
rad(Si)/s, when applied under recommended
operating conditions.
Neutron Radiation
The ROM will meet any functional or timing specification
after a total neutron fluence of up to 1x10
14
cm
-2
applied
under recommended operating or storage conditions. This
assumes an equivalent neutron energy of 1 MeV.
Single Event Phenomena
Transient Pulse Ionizing Radiation
The ROM is capable of reading and retaining stored data
during and after exposure to a transient ionizing radiation
pulse of
≤1 µs
duration up to 1x10
9
rad(Si)/s, when applied
under recommended operating conditions. To ensure va-
lidity of all specified performance parameters before, dur-
ing, and after radiation (timing degradation during tran-
sient pulse radiation (timing degradation during transient
pulse radiation is
≤10%),
it is suggested that stiffening
capacitance be placed on or near the package VDD and
VSS, with a maximum inductance between the package
(chip) and stiffening capacitance of 0.7 nH per part. If
there are no operate-through requirements, typical circuit
board mounted de-coupling capacitors are recommended.
All storage elements within the ROM are immune to single
event upsets. No access time or other performance deg-
radation will occur for LET 190 MeV/cm/mg
2
.
Latchup
The ROM will not latch up due to any of the above radiation
exposure conditions when applied under recommended
operating conditions. Fabrication with the SIMOX sub-
strate material provides oxide isolation between adjacent
PMOS and NMOS transistors and eliminates any potential
SCR latchup structures. Sufficient transistor body tie con-
nections to the p- and n-channel substrates are made to
ensure no source/drain snapback occurs.
RADIATION HARDNESS RATINGS (1)
Parameter
Total Dose
Transient Dose Rate Upset (3)
Transient Dose Rate Survivability (3)
Neutron Fluence
Limits (2)
≥1x10
6
≥1x10
9
≥1x10
11
≥1x10
14
Units
rad(SiO
2
)
rad(Si)/s
rad(Si)/s
N/cm
2
Test Conditions
T
A
=25°C
Pulse width
≤1 µs
Pulse width
≤50
ns, X-ray,
VDD=6.0 V, T
A
=25°C
1 MeV equivalent energy,
Unbiased, T
A
=25°C
(1) Device will not latch up due to any of the specified radiation exposure conditions.
(2) Operating conditions (unless otherwise specified): VDD=4.5 V to 5.5 V, TA=-55°C to 125°C.
(3) Not guaranteed with 28–Lead DIP.
3
HX6656
ABSOLUTE MAXIMUM RATINGS
(1)
Rating
Symbol
VDD
VPIN
TSTORE
TSOLDER
PD
IOUT
VPROT
Parameter
Positive Supply Voltage (2)
Voltage on Any Pin (2)
Storage Temperature (Zero Bias)
Soldering Temperature • Time
Total Package Power Dissipation (3)
DC or Average Output Current
ESD Input Protection Voltage (4)
28 FP/36 FP
Thermal Resistance (Jct-to-Case)
Junction Temperature
28 DIP
2000
2
10
175
Min
-0.5
-0.5
-65
Max
7.0
VDD+0.5
150
270•5
2.5
25
Units
V
V
°C
°C•s
W
mA
V
°C/W
°C
Θ
JC
TJ
(1) Stresses in excess of those listed above may result in permanent damage. These are stress ratings only, and operation at these levels is not
implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability.
(2) Voltage referenced to VSS.
(3) ROM power dissipation (IDDSB + IDDOP) plus ROM output driver power dissipation due to external loading must not exceed this specification.
(4) Class 2 electrostatic discharge (ESD) input protection. Tested per MIL-STD-883, Method 3015 by DESC certified lab.
RECOMMENDED OPERATING CONDITIONS
Description
Symbol
VDD
TA
VPIN
Parameter
Supply Voltage (referenced to VSS)
Ambient Temperature
Voltage on Any Pin (referenced to VSS)
Min
4.5
-55
-0.3
Typ
5.0
25
Max
5.5
125
VDD+0.3
Units
V
°C
V
CAPACITANCE
(1)
Symbol
CI
CO
Parameter
Input Capacitance
Output Capacitance
Typical
(1)
Worst Case
Min
Max
7
9
Units
pF
pF
Test Conditions
VI=VDD or VSS, f=1 MHz
VIO=VDD or VSS, f=1 MHz
(1) This parameter is tested during initial design characterization only.
4
HX6656
DC ELECTRICAL CHARACTERISTICS
Symbol
IDDSB1
Parameter
Static Supply Current
Typical Worst Case
(2)
Units
(1)
Min
Max
1.5
1.5
4.0
-1
-1
CMOS
TTL
CMOS
TTL
0.7xV
DD
Test Conditions
VIH=VDD IO=0
VIL=VSS Inputs Stable
NCS=VDD, IO=0,
f=40 MHz
f=1 MHz, IO=0, CE=VIH=VDD
NCS=VIL=VSS
VSS≤VI≤VDD
VSS≤VIO≤VDD
Output=high Z
mA
mA
mA
µA
µA
V
V
V
V
IDDSBMF Standby Supply Current - Deselected
IDDOPR
II
IOZ
VIL
Dynamic Supply Current, Selected
Input Leakage Current
Output Leakage Current
Low-Level Input Voltage
+1
+1
0.3xV
DD
0.8
VDD = 4.5V
VIH
High-Level Input Voltage
2.2
0.4
0.05
4.2
V
DD
-0.05
VDD = 5.5V
VDD = 4.5V, IOL = 10 mA
VDD = 4.5V, IOL = 200
µA
VDD = 4.5V, IOH = -5 mA
VDD = 4.5V, IOH = -200
µA
VOL
Low-Level Output Voltage
V
V
V
V
VOH
High-Level Output Voltage
(1) Typical operating conditions: VDD= 5.0 V,TA=25°C, pre-radiation.
(2) Worst case operating conditions: VDD=4.5 V to 5.5 V, -55°C to +125°C, post total dose at 25°C.
(3) All inputs switching. DC average current.
2.9 V
Vref1
249Ω
DUT
output
Vref2
+
-
Valid high
output
+
-
Valid low
output
CL >50 pF*
*CL = 5 pF for TWLQZ, TSHQZ, TELQZ, and TGHQZ
Tester Equivalent Load Circuit
5
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