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L74VHC1GT04DTT3

Description
Inverter, CMOS, PDSO5,
Categorylogic    logic   
File Size366KB,6 Pages
ManufacturerLRC
Websitehttp://www.lrc.cn
Download Datasheet Parametric View All

L74VHC1GT04DTT3 Overview

Inverter, CMOS, PDSO5,

L74VHC1GT04DTT3 Parametric

Parameter NameAttribute value
MakerLRC
package instructionTSOP, TSOP5/6,.11,37
Reach Compliance Codeunknow
JESD-30 codeR-PDSO-G5
Load capacitance (CL)50 pF
Logic integrated circuit typeINVERTER
MaximumI(ol)0.008 A
Number of terminals5
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP
Encapsulate equivalent codeTSOP5/6,.11,37
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
method of packingTAPE AND REEL
power supply3.3/5 V
Prop。Delay @ Nom-Su9.5 ns
Certification statusNot Qualified
Schmitt triggerNO
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal formGULL WING
Terminal pitch0.95 mm
Terminal locationDUAL
LESHAN RADIO COMPANY, LTD.
Inverting Buffer / CMOS Logic Level Shifter
with LSTTL–Compatible Inputs
L74VHC1GT04
The
L74VHC1GT04
is a single gate inverting buffer fabricated with silicon gate CMOS technology. It achieves high speed operation
similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output.
The device input is compatible with TTL–type input thresholds and the output has a full 5 V CMOS level output swing. The input
protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic–level translator from
3.0 V CMOS logic to 5.0V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the high–voltage power supply.
The
L74VHC1GT04
input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This
allows the
L74VHC1GT04
to be used to interface 5 V circuits to 3 V circuits. The output structures also provide protection when
V
CC
= 0 V. These input and output structures help prevent device destruction caused by supply voltage – input/output voltage mismatch,
battery backup, hot insertion, etc.
• High Speed: t
PD
= 3.8 ns (Typ) at V
CC
= 5 V
• Low Power Dissipation: I
CC
= 2 mA (Max) at T
A
= 25°C
• TTL–Compatible Inputs: V
IL
= 0.8 V; V
IH
= 2.0 V
• CMOS–Compatible Outputs: V
OH
> 0.8 V
CC
;
V
OL
< 0.1 V
CC
@Load
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
• Pin and Function Compatible with Other Standard Logic
Families
• Chip Complexity: FETs = 105; Equivalent Gates = 26
PIN ASSIGNMENT
MARKING DIAGRAMS
5
4
1
2
3
VK
d
SC–70/SC–88A/SOT–353
DF SUFFIX
Pin 1
d = Date Code
5
4
Figure 1. Pinout
(Top View)
1
2
3
VK
d
Figure 2. Logic Symbol
Pin 1
d = Date Code
SOT–23/TSOP–5/SC–59
DT SUFFIX
PIN ASSIGNMENT
1
2
3
4
5
NC
IN A
GND
OUT Y
V
CC
FUNCTION TABLE
Inputs
A
L
H
Output
Y
H
L
ORDERING INFORMATION
See detailed ordering and shipping information in the
package dimensions section on page 5 of this data sheet.
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