Am29PL160C
Data Sheet
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Publication Number
22143
Revision
C
Amendment
+4
Issue Date
June 12, 2002
Am29PL160C
16 Megabit (2 M x 8-Bit/1 M x 16-Bit)
CMOS 3.0 Volt-only High Performance Page Mode Flash Memory
DISTINCTIVE CHARACTERISTICS
■
16 Mbit Page Mode device
— Byte (8-bit) or word (16-bit) mode selectable via
BYTE# pin
— Page size of 16 bytes/8 words: Fast page read
access from random locations within the page
■
Single power supply operation
— Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
— Regulated voltage range: 3.0 to 3.6 volt read
and write operations and for compatibility with
high performance 3.3 volt microprocessors
■
5 V-tolerant data, address, and control signals
■
High performance read access times
— Page access times as fast as 25 ns at industrial
temperature range
— Random access times as fast as 65 ns
■
Power consumption (typical values at 5 MHz)
— 30 mA read current
— 20 mA program/erase current
— 1 µA standby mode current
— 1 µA Automatic Sleep mode current
■
Flexible sector architecture
— Sector sizes: One 16 Kbyte, two 8 Kbyte, one
224 Kbyte, and seven sectors of 256 Kbytes
each
— Supports full chip erase
■
Bottom boot block configuration only
■
Sector Protection
— A hardware method of locking a sector to prevent
any program or erase operations within that
sector
— Sectors can be locked via programming
equipment
— Temporary Sector Unprotect command
sequence allows code changes in previously
locked sectors
■
Minimum 1 million write cycles guarantee
per sector
■
20-year data retention
■
Manufactured on 0.32 µm process technology
■
Software command-set compatible with JEDEC
standard
— Backward compatible with Am29F and Am29LV
families
■
CFI (Common Flash Interface) compliant
— Provides device-specific information to the
system, allowing host software to easily
reconfigure for different Flash devices
■
Unlock Bypass Program Command
— Reduces overall programming time when
issuing multiple program command sequences
■
Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■
Package Options
— 44-pin SO (mask-ROM compatible pinout)
— 48-pin TSOP
This Data Sheet states AMD’s current specifications regarding the Products described herein. This Data Sheet may
be revised by subsequent versions or modifications due to changes in technical specifications.
Publication#
22143
Rev:
C
Amendment/+4
Issue Date:
June 12, 2002
Refer to AMD’s Website (www.amd.com) for the latest information.
GENERAL DESCRIPTION
The Am29PL160C is a 16 Mbit, 3.0 Volt-only Page
mode Flash memory device organized as 2,097,152
bytes or 1,048,576 words.The device is offered in a
44-pin SO or a 48-pin TSOP package. The word-wide
data (x16) appears on DQ15–DQ0; the byte-wide (x8)
data appears on DQ7–DQ0. This device can be pro-
grammed in-system or with in standard
EPROM programmers. A 12.0 V V
PP
or 5.0 V
CC
are
not required for write or erase operations.
The device offers access times of 65, 70, 90, and 120
ns, allowing high speed microprocessors to operate
without wait states. To eliminate bus contention the de-
vice has separate chip enable (CE#), write enable
(WE#), and output enable (OE#) controls.
The sector sizes are as follows: one 16 Kbyte, two
8 Kb yt e , o ne 2 24 K b yte an d se ven se ct or s o f
256 Kbytes each. The device is available in both top
and bottom boot versions.
verifies proper cell margin. The
Unlock Bypass
mode
facilitates faster programming times by requiring only
two write cycles to program data instead of four.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the
Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase,
the device automatically times the erase pulse widths
and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by reading the DQ7
(Data# Polling) and DQ6 (toggle)
status bits.
After a
program or erase cycle has been completed, the de-
vice is ready to read array data or accept another
command.
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of mem-
o r y. T h i s c a n b e a c h i e v e d i n - s y s t e m o r v i a
programming equipment.
The
Erase Suspend/Erase Resume
feature enables
the user to put erase on hold for any period of time to
read data from, or program data to, any sector that is
not selected for erasure. True background erase can
thus be achieved.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby
mode.
Power consumption is greatly reduced in both
these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.
Page Mode Features
The device is AC timing, pinout, and package
compat-
ible with 16 Mbit x 16 page mode Mask ROM.
The
page size is 8 words or 16 bytes.
After initial page access is accomplished, the page
mode operation provides fast read access speed of
random locations within that page.
Standard Flash Memory Features
The device requires only a
single 3.0 volt power sup-
ply
for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with
the
JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write cy-
cles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the
Embedded
Program
algorithm—an internal algorithm that
automatically times the program pulse widths and
2
Am29PL160C
June 12, 2002
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 7
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 8
Table 1. Am29PL160C Device Bus Operations ................................8
DQ5: Exceeded Timing Limits ................................................ 22
Figure 4. Toggle Bit Algorithm........................................................ 23
DQ3: Sector Erase Timer ....................................................... 23
Table 11. Write Operation Status ................................................... 24
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 25
Figure 5. Maximum Negative Overshoot Waveform ...................... 25
Figure 6. Maximum Positive Overshoot Waveform ........................ 25
Word/Byte Configuration .......................................................... 8
Requirements for Reading Array Data ..................................... 8
Read Mode ............................................................................... 8
Random Read (Non-Page Mode Read) ............................................8
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 25
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 7. I
CC1
Current vs. Time (Showing Active and Automatic
Sleep Currents) .............................................................................. 27
Figure 8. Typical I
CC1
vs. Frequency ............................................. 27
Page Mode Read ...................................................................... 9
Table 2. Word Mode ..........................................................................9
Table 3. Byte Mode ...........................................................................9
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 9. Test Setup....................................................................... 28
Table 12. Test Specifications ......................................................... 28
Writing Commands/Command Sequences ............................ 10
Program and Erase Operation Status .................................... 10
Standby Mode ........................................................................ 10
Automatic Sleep Mode ........................................................... 10
Output Disable Mode .............................................................. 10
Table 4. Sector Address Table, Bottom Boot (Am29PL160CB) ......11
Key to Switching Waveforms . . . . . . . . . . . . . . . 28
Figure 10. Input Waveforms and Measurement Levels ................. 28
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 11. Conventional Read Operations Timings .......................
Figure 12. Page Read Timings ......................................................
Figure 13. BYTE# Timings for Read Operations............................
Figure 14. BYTE# Timings for Write Operations............................
Figure 15. Program Operation Timings..........................................
Figure 16. AC Waveforms for Chip/Sector Erase Operations........
Figure 17. Data# Polling Timings (During Embedded Algorithms).
Figure 18. Toggle Bit Timings (During Embedded Algorithms)......
Figure 19. DQ2 vs. DQ6 for Erase and
Erase Suspend Operations ............................................................
Figure 20. Alternate CE# Controlled Write Operation Timings ......
30
30
31
31
33
34
34
35
35
37
Autoselect Mode ..................................................................... 12
Table 5. Am29PL160C Autoselect Codes (High Voltage Method) ..12
Sector Protection/Unprotection ............................................... 12
Common Flash Memory Interface (CFI) . . . . . . . 13
Table 6. CFI Query Identification String ..........................................13
Table 7. System Interface String .....................................................14
Table 8. Device Geometry Definition ..............................................14
Table 9. Primary Vendor-Specific Extended Query ........................15
Hardware Data Protection . . . . . . . . . . . . . . . . . . 15
Low V
CC
Write Inhibit ......................................................................15
Write Pulse “Glitch” Protection ........................................................15
Logical Inhibit ..................................................................................15
Power-Up Write Inhibit ....................................................................15
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 16
Reading Array Data ................................................................ 16
Reset Command ..................................................................... 16
Autoselect Command Sequence ............................................ 16
Word/Byte Program Command Sequence ............................. 16
Unlock Bypass Command Sequence ..............................................17
Figure 1. Program Operation .......................................................... 17
Chip Erase Command Sequence ........................................... 17
Sector Erase Command Sequence ........................................ 18
Erase Suspend/Erase Resume Commands ........................... 18
Temporary Unprotect Enable/Disable Command Sequence .. 19
Figure 2. Erase Operation............................................................... 19
Command Definitions ............................................................. 20
Table 10. Am29PL160C Command Definitions ..............................20
Write Operation Status . . . . . . . . . . . . . . . . . . . . 21
DQ7: Data# Polling ................................................................. 21
Figure 3. Data# Polling Algorithm ................................................... 21
DQ6: Toggle Bit ...................................................................... 22
DQ2: Toggle Bit ...................................................................... 22
Reading Toggle Bits DQ6/DQ2 .............................................. 22
Erase and Programming Performance . . . . . . . 38
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 38
TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 38
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 39
TS 048—48-Pin Standard Thin Small Outline Package ......... 39
SO 044—44-Pin Small Outline Package, Standard Pinout .... 40
SOR044—44-Pin Small Outline Package, Reverse Pinout .... 41
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 42
Revision A (August 1998) ....................................................... 42
Revision A+1 (September 1998) ............................................ 42
Revision B (January 1999) ..................................................... 42
Revision B+1 (February 1999) ................................................ 42
Revision B+2 (March 5, 1999) ................................................ 42
Revision B+3 (May 14, 1999) ................................................. 42
Revision B+4 (June 25, 1999) ................................................ 42
Revision B+5 (July 26, 1999) .................................................. 42
Revision B+6 (September 2, 1999) ........................................ 42
Revision B+7 (February 4, 2000) ............................................ 42
Revision C (February 21, 2000) .............................................. 42
Revision C+1 (June 20, 2000) ................................................ 42
Revision C+2 (June 28, 2000) ................................................ 42
Revision C+3 (November 14, 2000) ....................................... 42
Revision C+4 (June 12, 2002) ................................................ 42
June 12, 2002
Am29PL160C
3
PRODUCT SELECTOR GUIDE
Family Part Number
Speed Option
Regulated Voltage Range: V
CC
=3.0–3.6 V
Full Voltage Range: V
CC
= 2.7–3.6 V
Max access time, ns (t
ACC
)
Max CE# access time, ns (t
CE
)
Max page access time, ns (t
PACC
)
Max OE# access time, ns (t
OE
)
Note:
See “AC Characteristics” for full specifications.
65
65
25
25
70
70
25
25
-65R
Am29PL160C
-70R
-90
90
90
30
30
-120
120
120
30
30
BLOCK DIAGRAM
DQ0
–
DQ15
V
CC
V
SS
Erase Voltage
Generator
Input/Output
Buffers
WE#
BYTE#
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Data
Latch
CE#
OE#
STB
V
CC
Detector
Timer
Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0–A19
A-1
4
Am29PL160C
June 12, 2002
Domestic Chip Exchange
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