ICM7555
General purpose CMOS timer
Rev. 02 — 3 August 2009
Product data sheet
1. General description
The ICM7555 is a CMOS timer providing significantly improved performance over the
standard NE/SE555 timer, while at the same time being a direct replacement for those
devices in most applications. Improved parameters include low supply current, wide
operating supply voltage range, low THRESHOLD, TRIGGER, and RESET currents, no
crowbarring of the supply current during output transitions, higher frequency performance
and no requirement to decouple CONTROL_VOLTAGE for stable operation.
The ICM7555 is a stable controller capable of producing accurate time delays or
frequencies.
In the one-shot mode, the pulse width of each circuit is precisely controlled by one
external resistor and capacitor. For astable operation as an oscillator, the free-running
frequency and the duty cycle are both accurately controlled by two external resistors and
one capacitor. Unlike the NE/SE555 device, the CONTROL_VOLTAGE terminal need not
be decoupled with a capacitor. The TRIGGER and RESET inputs are active LOW. The
output inverter can source or sink currents large enough to drive TTL loads or provide
minimal offsets to drive CMOS loads.
2. Features
I
I
I
I
I
I
I
I
I
I
I
I
I
Exact equivalent in most applications for NE/SE555
Low supply current: 80
µA
(typical)
Extremely low trigger, threshold, and reset currents: 20 pA (typical)
High-speed operation: 500 kHz guaranteed
Wide operating supply voltage range guaranteed 3 V to 16 V over full automotive
temperatures
Normal reset function; no crowbarring of supply during output transition
Can be used with higher-impedance timing elements than the NE/SE555 for longer
time constants
Timing from microseconds through hours
Operates in both astable and monostable modes
Adjustable duty cycle
High output source/sink driver can drive TTL/CMOS
Typical temperature stability of 0.005 % /
°C
at 25
°C
Rail-to-rail outputs
NXP Semiconductors
ICM7555
General purpose CMOS timer
3. Applications
I
I
I
I
I
I
I
Precision timing
Pulse generation
Sequential timing
Time delay generation
Pulse width modulation
Pulse position modulation
Missing pulse detector
4. Ordering information
Table 1.
Ordering information
Temperature range
T
amb
= 0
°C
to +70
°C
T
amb
=
−40 °C
to +85
°C
T
amb
= 0
°C
to +70
°C
T
amb
=
−40 °C
to +85
°C
DIP8
plastic dual in-line package; 8 leads (300 mil)
SOT97-1
Package
Name
ICM7555CD
ICM7555ID
ICM7555CN
ICM7555IN
SO8
Description
plastic small outline package; 8 leads; body width 3.9 mm
Version
SOT96-1
Type number
5. Functional diagram
flip-flop
V
DD
8
R
comparator A
6
THRESHOLD
5
CONTROL_VOLTAGE
R
comparator B
TRIGGER
2
R
1
GND
DISCHARGE
7
N
1
GND
RESET
4
output
drivers
3
OUTPUT
002aae403
Remark:
Unused inputs should be connected to appropriate voltage from
Table 3.
Fig 1.
Functional diagram
ICM7555_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 3 August 2009
2 of 22
NXP Semiconductors
ICM7555
General purpose CMOS timer
6. Pinning information
6.1 Pinning
GND
TRIGGER
OUTPUT
RESET
1
2
3
4
002aae400
8
V
DD
GND
TRIGGER
OUTPUT
RESET
1
8
V
DD
DISCHARGE
THRESHOLD
CONTROL_VOLTAGE
ICM7555CD
7 DISCHARGE
ICM7555ID
6 THRESHOLD
5
CONTROL_VOLTAGE
2
ICM7555CN
7
3
4
002aae401
ICM7555IN
6
5
Fig 2.
Pin configuration for SO8
Fig 3.
Pin configuration for DIP8
6.2 Pin description
Table 2.
Symbol
GND
TRIGGER
OUTPUT
RESET
CONTROL_VOLTAGE
THRESHOLD
DISCHARGE
V
DD
Pin description
Pin
1
2
3
4
5
6
7
8
Description
supply ground
start timer input; (active LOW)
timer logic level output
timer inhibit input; (active LOW)
timing capacitor upper voltage sense input
timing capacitor lower voltage sense input
timing capacitor discharge output
supply voltage
7. Functional description
Refer to
Figure 1 “Functional diagram”.
7.1 Function selection
Table 3.
don’t care
>
2
⁄
3
V+
V
th
<
2
⁄
3
V+
don’t care
[1]
Function selection
TRIGGER voltage
don’t care
>
1
⁄
3
V+
V
trig
>
1
⁄
3
V+
<
1
⁄
3
V+
RESET
[1]
L
H
H
H
OUTPUT
L
L
stable
H
Discharge switch
on
on
stable
off
THRESHOLD voltage
RESET will dominate all other inputs; TRIGGER will dominate over THRESHOLD.
ICM7555_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 3 August 2009
3 of 22
NXP Semiconductors
ICM7555
General purpose CMOS timer
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DD
V
I
Parameter
supply voltage
input voltage
TRIGGER
CONTROL_VOLTAGE
THRESHOLD
RESET
I
O
P
output current
power dissipation
T
amb
= 25
°C
(still air)
DIP8 package
SO8 package
T
stg
T
sp
[1]
[2][3]
[1]
Conditions
Min
−0.3
−0.3
−0.3
−0.3
-
-
-
−65
-
Max
18
V
DD
+ 0.3
V
DD
+ 0.3
V
DD
+ 0.3
V
DD
+ 0.3
100
1160
780
+150
300
Unit
V
V
V
V
V
mA
mW
mW
°C
°C
storage temperature
solder point temperature
soldering 60 s
Due to the SCR structure inherent in the CMOS process used to fabricate these devices, connecting any terminal to a voltage greater
than V
DD
+ 0.3 V or less than GND
−
0.3 V may cause destructive latch-up. For this reason it is recommended that no inputs from
external sources not operating from the same power supply be applied to the device before its power supply is established. In multiple
systems, the supply of the ICM7555 must be turned on first.
Above 25
°C,
derate at the following rates:
DIP8 package at 9.3 mW /
°C
SO8 package at 6.2 mW /
°C
Refer to
Section 11.2 “Power supply considerations”
section.
[2]
[3]
9. Characteristics
Table 5.
Characteristics
T
amb
= 25
°
C unless otherwise specified.
Sym
bol
V
DD
I
DD
Parameter
supply voltage
supply current
[1]
Conditions
T
min
≤
T
amb
≤
T
max
V
DD
= V
min
V
DD
= V
max
Astable mode timing
[2][3]
∆f/f
frequency stability
V
DD
= 5 V
V
DD
= 10 V
V
DD
= 15 V
V
I
input voltage
TRIGGER: V
DD
= 5 V
CONTROL_VOLTAGE: V
DD
= 5 V
THRESHOLD: V
DD
= 5 V
RESET: V
DD
= V
min
and V
max
-
-
-
-
-
0.29V
DD
0.62V
DD
0.63V
DD
0.4V
DD
1.0
0.1
50
75
100
0.31V
DD
0.65V
DD
0.65V
DD
0.7V
DD
5.0
3.0
-
-
-
0.34V
DD
0.67V
DD
0.67V
DD
1.0V
DD
%
%/V
ppm/°C
ppm/°C
ppm/°C
V
V
V
V
∆f/∆V
frequency variation with voltage
∆f/∆T
frequency variation with
temperature
[4]
Min
3
-
-
Typ
-
50
180
Max
16
200
300
Unit
V
µA
µA
ICM7555_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 3 August 2009
4 of 22
NXP Semiconductors
ICM7555
General purpose CMOS timer
Table 5.
Characteristics
…continued
T
amb
= 25
°
C unless otherwise specified.
Sym
bol
I
I
Parameter
input current
Conditions
TRIGGER
V
DD
= V
trig
= V
max
V
DD
= V
trig
= 5 V
V
DD
= V
trig
= V
min
THRESHOLD
V
DD
= V
th
= V
max
V
DD
= V
th
= 5 V
V
DD
= V
th
= V
min
RESET
V
DD
= V
rst
= V
max
V
DD
= V
rst
= 5 V
V
DD
= V
rst
= V
min
V
OL
V
OH
LOW-level output voltage
HIGH-level output voltage
V
DD
= V
max
; I
sink
= 3.2 mA
V
DD
= 5 V; I
sink
= 3.2 mA
I
source
=
−1.0
mA
V
DD
= V
max
V
DD
= 5 V
max
V
o
t
r(o)
t
f(o)
f
osc
[1]
[2]
Min
Typ
Max
Unit
-
-
-
-
-
-
-
-
-
-
-
15.25
4.0
-
-
-
50
10
1
50
10
1
100
20
2
0.1
0.2
15.7
4.5
0.2
45
20
-
-
-
-
-
-
-
-
-
-
0.4
0.4
-
-
0.4
75
75
500
pA
pA
pA
pA
pA
pA
pA
pA
pA
V
V
V
V
V
ns
ns
kHz
output voltage
output rise time
[4]
output fall time
[4]
oscillator frequency
DISCHARGE:
V
DD
= 5 V; I
DIS
= 10 mA
R
L
= 10 MΩ; C
L
= 10 pF;
V
DD
= 5 V
astable mode
-
The supply current value is essentially independent of the TRIGGER, THRESHOLD and RESET voltages.
Astable timing is calculated using the following equation:
1.38
f
=
--------------------------------
-
(
R
A
+
2R
B
)C
The components are defined in
Figure 15.
[3]
[4]
R
A
, R
B
= 1 kΩ to 100 kΩ; C = 0.1
µF;
5 V < V
DD
< 15 V
Parameter is not 100 % tested.
ICM7555_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 3 August 2009
5 of 22
PCB Design
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