MB9AA40NA Series
32-bit ARM
TM
Cortex
TM
-M3 based Microcontroller
MB9AFA41LA/MA/NA, MB9AFA42LA/MA/NA,
MB9AFA44LA/MA/NA
Data Sheet (Full Production)
Publication Number MB9AA40NA_DS706-00038
Revision 2.1
Issue Date January 31, 2014
D a t a S h e e t
2
MB9AA40NA_DS706-00038-2v1-E, January 31, 2014
MB9AA40NA Series
32-bit ARM
TM
Cortex
TM
-M3 based Microcontroller
MB9AFA41LA/MA/NA, MB9AFA42LA/MA/NA,
MB9AFA44LA/MA/NA
Data Sheet (Full Production)
DESCRIPTION
The MB9AA40NA Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers
with low-power consumption mode and competitive cost.
These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and have
peripheral functions such as various timers, ADCs, LCDC and Communication Interfaces (UART, CSIO,
I
2
C).
The products which are described in this data sheet are placed into TYPE6 product categories in "FM3
Family PERIPHERAL MANUAL".
Note: ARM and Cortex are the trademarks of ARM Limited in the EU and other countries.
Publication Number MB9AA40NA_DS706-00038
Revision 2.1
Issue Date January 31, 2014
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient
production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the
valid combinations offered may occur.
D a t a S h e e t
FEATURES
32-bit ARM Cortex-M3 Core
Processor version: r2p1
Up to 40 MHz Frequency Operation
Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and
48 peripheral interrupts and 16 priority levels
24-bit System timer (Sys Tick): System timer for OS task management
On-chip Memories
[Flash memory]
Dual operation Flash memory
・Dual
Operation Flash memory has the upper bank and the lower bank.
So, this series could implement erase, write and read operations
for each bank simultaneously.
Main area: Up to 256 Kbytes (Up to 240Kbytes upper bank + 16Kbytes lower bank)
Work area: 32 Kbytes (lower bank)
Read cycle: 0 wait-cycle
Security function for code protection
[SRAM]
This Series on-chip SRAM is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is
connected to I-code bus or D-code bus of Cortex-M3 core. SRAM1 is connected to System bus.
SRAM0: Up to 16 Kbytes
SRAM1: Up to 16 Kbytes
External Bus Interface*
Supports SRAM, NOR Flash memory device
Up to 8 chip selects
8/16-bit Data width
Up to 25-bit Address bit
Supports Address/Data multiplex
Supports external RDY function
* : MB9AFA41LA, FA42LA and FA44LA do not support External Bus Interface.
LCD
Controller
(LCDC)
Up to 40 SEG × 8COM
8COM or 4COM mode can be selected.
Built-in internal dividing resistor
LCD drive power supply (bias) pin (VV4 to VV0)
With blinking function
2
MB9AA40NA_DS706-00038-2v1-E, January 31, 2014
D a t a S h e e t
Multi-function Serial Interface (Max 8channels)
4 channels with 16steps×9-bit FIFO (ch.4 to ch.7), 4 channels without FIFO (ch.0 to ch.3)
Operation mode is selectable from the followings for each channel.
UART
CSIO
I
2
C
[UART]
Full-duplex double buffer
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Hardware Flow control* : Automatically control the transmission by CTS/RTS (only ch.4)
Various error detection functions available (parity errors, framing errors, and overrun errors)
* : MB9AFA41LA, FA42LA and FA44LA do not support Hardware Flow control.
[CSIO]
Full-duplex double buffer
Built-in dedicated baud rate generator
Overrun error detection function available
[I C]
Standard mode (Max 100kbps) / High-speed mode (Max 400kbps) supported
DMA Controller (8channels)
The DMA Controller has an independent bus from the CPU, so CPU and DMA Controller can process
simultaneously.
8 independently configured and operated channels
Transfer can be started by software or request from the built-in peripherals
Transfer address area: 32-bit (4 Gbytes)
Transfer mode: Block transfer/Burst transfer/Demand transfer
Transfer data type: byte/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
2
A/D Converter (Max 24channels)
[12-bit A/D Converter]
Successive Approximation type
Built-in 2units
Conversion time: 2.0μs @ 2.7V to 3.6V
Priority conversion available (priority at 2levels)
Scanning conversion mode
Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion:
4steps)
Base Timer (Max 8channels)
Operation mode is selectable from the followings for each channel.
16-bit PWM timer
16-bit PPG timer
16/32-bit reload timer
16/32-bit PWC timer
January 31, 2014, MB9AA40NA_DS706-00038-2v1-E
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