1. Flash memory devices in BGA packages can be damaged if exposed to ultrasonic cleaning methods. The package, data integrity, or both may be compromised if the
package body is exposed to temperatures above 150 °C for prolonged periods of time.
Document Number: 002-23879 Rev. *A
Page 3 of 9
S26HS256T/S26HS512T/S26HS01GT
S26HL256T/S26HL512T/S26HL01GT
Table 1. Signal Description
Symbol
CS#
Type
Input
Mandatory /
Optional
Description
Mandatory
Chip Select (CS#).
All bus transactions are initiated with a HIGH to LOW transition on
CS# and terminated with a LOW to HIGH transition on CS#. Driving CS# LOW enables
the device, placing it in the Active mode. When CS# is driven HIGH, the device enters
Standby mode, unless an internal embedded operation is in progress. All other input
pins are ignored and the output pins are put in HIGH impedance state.
Mandatory
Clock (CK, CK#).
Clock provides the timing of the serial interface. Single ended and
differential clock modes are offered. Transactions are latched either on the rising edge
of CK signal (single ended) or on the crossing of the CK and CK# signals (differential).
In Legacy (×1) SPI interface, command, address and data inputs are latched on rising
edge of the clock, and data is output on the falling edge of the clock.
In HyperBus (×8) interface, for single ended clock, command, address and data input
are latched with respect to the rising and falling edge of the CK. In differential clock
mode, command, address and data inputs are latched with respect to the crossing of
CK and CK#.
Differential Clock.
CK and CK# are used.
Single Ended:
CK is used (CK# is not used and can be left floating).
Mandatory
Read Data Strobe (DS).
DS is used for data read operations only and indicates output
data valid for HyperBus interface. During a read transaction while CS# is LOW, DS
toggles to synchronize data output until CS# goes HIGH. Output data during read trans-
actions are edge aligned with DS.
Mandatory
Serial Data (DQ[7:0]).
Bidirectional signals that transfer command, address and data
information.
Legacy (x1) SPI Interface:
DQ[0] is an input (SI) and DQ[1] is an output (SO).
HyperBus (x8) Interface:
DQ[7:0] are input and output.
Optional
Hardware Reset (RESET#).
When Low, the device will self initialize and return to the
array read state. DS and DQ[7:0] are placed into the High-Z state when RESET# is Low.
RESET# includes a weak pull-up, meaning, if RESET# is left unconnected it will be
pulled up to the High state.
System Interrupt (INT#).
When LOW, the device is indicating that an internal event has
occurred. This signal is intended to be used as a system level interrupt for the device
to indicate that an on-chip event has occurred. INT# is an open-drain output.
Reset Output (RSTO#).
RSTO# is an open-drain output used to indicate when a POR
is occurring within the device and can be used as a system level reset signal. Upon
completion of the internal POR the RSTO# signal will transition from Low to high
impedance after a user defined timeout period has elapsed. Upon transition to the high
impedance state the external pull-up resistance will pull RSTO# High and the device
immediately is placed into the Standby state. Transactions are blocked when RSTO# is
LOW. During this period, the device cannot be selected, will not accept any transactions,
and does not drive outputs other than RSTO#.
CK, CK#
[2, 3]
Input
DS
Output
DQ[7:0]
Input/Output
RESET#
Input (Weak
Pull-up)
INT#
Output
(Open Drain)
Output
(Open Drain)
Optional
RSTO#
Optional
V
CC
V
CCQ
V
SS
V
SSQ
DNU
Power Supply
Power Supply
Mandatory Core Power Supply
Mandatory Input / Output Power Supply
Ground Supply Mandatory Core Ground
Ground Supply Mandatory Input / Output Ground
–
–
Do Not Use.
Notes
2. The clock is not required to be free running.
3. CK and CK# are not true differential signals. They are compliment signals. Care must be taken to ensure system level terminations are properly designed in.
Document Number: 002-23879 Rev. *A
Page 4 of 9
S26HS256T/S26HS512T/S26HS01GT
S26HL256T/S26HL512T/S26HL01GT
General Description
The Cypress Semper Flash family of products are high-speed CMOS, MirrorBit
NOR flash devices that are compliant with the JEDEC
JESD251 eXpanded SPI (xSPI) specification. Semper Flash is designed for Functional Safety with development according to ISO
26262 standard to achieve ASIL-B compliance and ASIL-D readiness.
Semper Flash with HyperBus Interface devices support both the HyperBus Interface as well as Legacy (x1) SPI. Both interfaces
serially transfer transactions reducing the number of interface connection signals. SPI supports SDR whereas HyperBus supports
DDR.
The HyperBus interface (DDR) transfers two data bytes per clock cycle on the data (DQ) signals. A read or program/write access
consists of a series of 16-bit wide, one clock cycle data transfers at the internal HyperFlash core and two corresponding 8-bit wide,
one-half-clock-cycle data transfers on the DQ signals. Both data and command/address information are transferred in DDR fashion
over the 8-bit data bus. The clock input signals are used for signal capture by Semper Flash when receiving command/address/data
information on the DQ signals. The Read Data Strobe (DS) is an output from Semper Flash that indicates when data is being
transferred from the memory. DS is referenced to the rising and falling edges of CK during the data transfer portion of read
operations. Command/address/write-data values are center aligned with the clock edges and read-data values are edge aligned
with the transitions of DS.
Read and program/write operations to Semper Flash are burst oriented. Read transactions can be specified to use either a wrapped
or linear burst. During wrapped operation, accesses start at a selected location and continue for a configured number of locations in
a group wrap sequence. During linear operation accesses start at a selected location and continue in a sequential manner until the
read operation is terminated, when CS# returns HIGH. Write transactions transfer one or more16-bit values.
Each random read accesses a 32-Byte length and aligned set of data called a page. Each page consists of a pair of 16-Byte aligned
groups of array data called half-pages. Half-pages are aligned on 16-Byte address boundaries. A read access requires two clock
cycles to define the target half-page address and the burst type, then an additional initial latency. During the initial latency period the
third clock cycle will specify the starting address within the target half-page. After the initial data value has been output, additional
data can be read from the Page on subsequent clock cycles in either a wrapped or linear manner. When configured in linear burst
mode, while a page is being burst out, the device will automatically fetch the next sequential page from the MirrorBit flash memory
array. This simultaneous burst output while fetching from the array allows for a linear sequential burst operation that can provide a
sustained output of 400/333 MBps data rate
[1-Byte (8-bit data bus) * 2 (Data on both clock edges) * 200/166 MHz = 400/333 MBps]
The erased state of each memory bit is a logic 1. Programming changes a logic 1 (HIGH) to a logic 0 (LOW). Only an erase operation
can change a memory bit from a 0 to a 1. An erase operation must be performed on a complete sector (4 KBs or 256 KBs).
Semper Flash provides a flexible sector architecture. The address space can be configured as either a uniform 256 KB sector array,
or a hybrid configuration 1 array where thirty-two 4 KB sectors are either at the top or at the bottom while the remaining sectors are
all 256 KB, or a hybrid configuration 2 array where the thirty-two 4 KB sectors are equally split between the top and the bottom while
the remaining sectors are all 256 KB.
The Page Programming Buffer used during a single programming operation is configurable to either 256 bytes or 512 bytes. The
512 byte option provides the highest programming throughput.
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