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1.32 Gbit/s Serial Link
Transmitter and Receiver
The GigaSTaR (Gigabit/s
Serial Transmitter and Receiver)
is a universal high-speed point-to-point communication link.
It consists of two devices, the Transmitter INGT165B and the
Receiver INGR165B.
The INGT165B Transmitter converts parallel data up to 36-bit to
a serial bit-stream. The differential CML (Current Mode Logic)
outputs can directly drive Shielded-Twisted-Pair (STP) cables
for distances up to 50 meters and can directly interface to inputs
of fiber optic modules to span longer distances.
The INGR165B Receiver converts the serial bit-stream to the
original parallel data format, fully transparent and without
protocol overhead.
Link-synchronization, bit-stream coding/decoding, clock-/frame-
recovery and parity-check are managed by internal high-speed
resources.
GigaSTaR
®
links can be operated in parallel, scaling the
bandwidth in multiples of 1.188 Gbit/s (payload data rate).
®
INGT165B
INGR165B
INGT165B
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INGR165B
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12x12 mm, 196 PBGA packages
FEATURES
36-bit 33 MHz parallel data interface (3.3V CMOS)
Variable payload data transfer rate up to 1.188 Gbit/s
Internal RF clock-generation and clock-recovery (PLL)
Integrated DC-balanced coding for AC coupling
Integrated cable equalizer (INGR165B)
Built in parity check
Low latency of 40 ns per device (type)
Differential, low-swing CML-signals for the serial link
High signal robustness, EMI and noise immunity
Direct interfacing to 50/100 Ohm cables
and fiber optic modules
Single +3.3V DC supply
Low power dissipation of 1 W per device (type)
Ambient operating temperature – 40°C to +85° C
APPLICATIONS
High-speed scanning / printing
(photo, exposure- and security
systems)
Mass storage connections
High-speed and multi-channel
imaging
Telecommunication switches
High-speed sensors / actuators
Industrial Control
High-resolution panel links
Data broadcast (Video Server)
¡
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RDCLK
¢
WRCLK
GigaST#R
Transmitter
INGT165B
¢
PDATA[35..0]
GigaST#R
Receiver
INGR165B
PDATA[35..0]
Figure 1: GigaSTaR
®
Link
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INGT165B / INGR165B
1. GigaSTaR
®
LINK DESCRIPTION
The GigaSTaR
®
link is designed for reliable, high-speed, low-latency data transmission.
All functions for data transfer management including the high-frequency blocks are fully integrated in the
Transmitter and Receiver devices. Both devices feature a 36-bit “user-friendly” parallel interface with
standard logic levels (3.3V CMOS) for easy adaptation to any application.
The link supports an effective (sustained) data rate up to 148.5 MByte/s at the parallel interface, which
translates to a serial bit stream of max. 1.188 Gbit/s (payload data rate). With 4 additional bits for link-
synchronization, DC-balancing and parity check the maximum bit rate at the serial I/Os is 1.32Gbit/s, for an
overall link efficiency of 90 percent. With only 40 ns propagation delay time each for the Transmitter and
Receiver, the typical overall latency for a GigaSTaR
®
link with STP copper cable is:
latency [ns] = 2 * 40 ns + 4ns/m * cable-length [m]
For example, the latency is about 160 ns for a 20 meter connection with Shielded-Twisted-Pair (STP)
copper cable.
1.1 CLOCK SYSTEM
The serial bit clock frequency of 1320 MHz is generated by internal PLLs. The Transmitter and Receiver
each require an external 66 MHz reference clock.
A continuous phase alignment in the Receiver ensures that the receive clock is synchronous to the
transmit clock.
1.2 PARALLEL DATA FORMAT
Both the GigaSTaR
®
Transmitter and Receiver feature a synchronous 36 bit parallel interface. The
maximum frequency at this interface is 33 MHz, equivalent to a period of 30.3 ns for the WRCLK/ RDCLK
signals.
Additional parity I/Os allow the transfer of an optional external parity bit synchronous with the parallel data.
If an external parity bit is provided, the Transmitter validates the signal before the start of the transmission.
If no external parity bit is available, the Transmitter generates this signal automatically.
Parity error flags are provided at both the Transmitter and Receiver devices.
1.3 SERIAL DATA FORMAT
The serial data stream is DC-balanced to support capacitive (AC) coupling for full DC isolation of the link.
This is performed by proprietary coding in the Transmitter device.
1.4 LINK MEDIA (COPPER OR FIBER)
The GigaSTaR
®
Transmitter and Receiver are each equipped with a robust high-speed interface which can
be directly connected to impedance-controlled cables (STP or coax), transmission lines or fiber optic
modules.
Initial evaluations with 50 Ohm (100 Ohm differential) Shielded-Twisted-Pair (STP) cables already have
proven reliable transmissions at distances of up to 50 meters and beyond (Reference-product:
GGSC1608-05/-10/-15/-20/-30/-40/-50, W.L. Gore & Associates).
Copper media require a serial line termination (R/L combination) at the inputs of the GigaSTaR
®
Receiver
for optimized performance, please refer to the ING_TRC piggyback board data sheet for reference values.
The capacitors for AC coupling of the serial lines have to be 100nF and are to be applied at both ends of
the link medium (see also figure 1). It is required to use ceramic RF capacitors.
With conventional 850 nm fiber optic modules (AC in/out, 3.3V PECL) and multimode fiber distances up to
550 meters have been achieved, see also datasheet of the ING_TRF fiberoptical piggyback board.
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INGT165B / INGR165B
2. GigaSTaR
®
INGT165B TRANSMITTER
2.1 BLOCK DIAGRAM
OSC
LOCK
EXTRC1
EXTRC2
1.32 GHz
CLOCK GENERATOR
RDCLK
PDATA[35..0]
PARITY
VALID
CLOCK
Tx_SHIFTER
FRAMER
SERIALIZER
SDATA
SDATA#
SHIFTER
CTRL
HEADER
MUX CTRL
(FLOW CONTROL & HEADER GENERATOR )
RESET#
PERR#
PARGEN
FLAGI
SYNGEN
Figure 2: GigaSTaR
®
Transmitter Block Diagram
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INGT165B / INGR165B
2.2 INGT165B TRANSMITTER PARALLEL INTERFACE
The Transmitter parallel interface is designed to support different operating modes providing a maximum
flexibility for the design of the application interface.
RESET#
LOCK
SYNGEN
£
PARGEN
FLAGI
VALID
RDCLK
PDATA[35..0]
PARITY
PERR#
GigaST#R
INGT165B
TRANSMITTER
SDATA
SDATA#
Figure 3: GigaSTaR
®
Transmitter Parallel Interface
2.2.1 Control Signals
RESET# is an asynchronous active low reset signal. After a power-up sequence and activation of the
reference clock, RESET# has to be kept low for at least 1 ms. The link is operational as soon as the
LSYNC# signal of the Receiver is going low.
LOCK = '1' indicates that the internal PLL is locked. If LOCK is de-asserted the Transmitter is not ready.
PARGEN = '1' activates the internal parity generation. In this mode the PARITY input pin is ignored.
An internal parity bit is generated and transmitted.
The positive edge of FLAGI sets an internal flag which is inserted at the end of the data word currently in
transmission. The Receiver decodes the flag out of the serial bit-stream and toggles the level of the
FLAGO output. This signal can be used to mark the end of a data frame.
VALID = '1' indicates to the Transmitter that data are available. With the assertion of VALID the RDCLK
starts to run. PDATA[35..0] is registered at each rising edge of RDCLK. De-asserting VALID disables
RDCLK and stuffing patterns are transmitted over the GigaSTaR
®
link to maintain synchronization.
PERR#: description see 2.2.2
Note: the SYNGEN input is reserved for optional functions and has to be set to “0”.
2.2.2 Data Interface
The GigaSTaR
®
parallel data interface is designed to support a variety of application interfaces.
It provides read clock (RDCLK) pulses with a cycle time of 30,3 ns (corresponding to 33MHz) to the
application output buffers like FIFOs, memory devices, ASICs or PLDs.
A data word at the parallel interface consists of 36 data bits. If PARGEN = '0' the transmitting application
has to supply the data's parity at the input PARITY synchronous to the parallel data. PARGEN = '1' logic
high activates internal parity generation and the PARITY input pin is ignored. If the application supplies its
own parity bit (PARGEN is de-asserted), PERR# reports any mismatch between the internally generated
and the external PARITY signal. If this is the case, the internally generated (correct) PARITY is transmitted
with the data word. PERR# is always inactive when PARGEN = '1'. The default value of PERR# after reset
is ‘1’.
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INGT165B / INGR165B
2.2.3 Data Burst Transfers
The data burst timing provides the full data rate of 148.5 MByte/s. VALID is asserted when the first data is
valid at PDATA[35.0]. With every rising edge of RDCLK the PDATA inputs are registered, serialized and
transmitted. VALID can remain asserted as long as new data are available.
In the timing diagram PARGEN is de-asserted and the application delivers the PARITY bit synchronously
to the data word.
LOCK#
RESET#
t
2-2
t
2-1
t
5
t
5
VALID
RDCLK
PDATA [35..0]
PARITY
DW1
PARITY1
DW2
PARITY2
DW3
PARITY3
t
2
t
1
t
3
t
4
Figure 4: INGT165B Data Burst Timing Diagram
Parameter
t
1
t
2
t
2-1
t
2-2
t
3
t
4
t
5
Description
Setup time PDATA and PARITY to RDCLK rising edge
VALID active to first rising RDCLK edge
VALID high state
LOCK# / RESET# high state before Tx operational *
PDATA and PARITY hold time
RDCLK cycle time (without assertion of FLAGI)
Rising RDCLK edge to sampling window for VALID state
(VALID=0: exit BURST mode,
VALID=1: continue BURST mode)
Min.
9
9
5
50
9
18
Typ.
6
12
4
6
30.3
20
Max.
14
Unit
ns
ns
ns
µs
ns
ns
ns
22
Note : For timings with assertion of FLAGI, please see section 3.2.5
*A dislock pulse generates an internal transmitter reset. Therefore both signals have to be at least
50us at high state before transmitter is operational.
Table 1: INGT165B Data Burst Timing Parameters (under recommended operating conditions)
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