IP175C-DS-R05 datasheet, PDF - EEWORLD Datasheet

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IP175C-DS-R05: Description5 Port 10/100 Ethernet Integrated Switch; File Size693KB，111 Pages; ManufacturerETC2

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IP175C-DS-R05 Overview

5 Port 10/100 Ethernet Integrated Switch

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IP175C/IP175C LF/IP175CH/IP175CH LF

Data Sheet

5 Port 10/100 Ethernet Integrated Switch

Features

General Description

IP175A PCB compatible (pins compatible)

IP175C/IP175CH integrates a 6-port switch

Built in 6 MAC and 5 PHY

controller, SSRAM, and 5 10/100 Ethernet

Each port can be configured to be 10Base-T, transceivers. Each of the transceivers complies with

100Base-TX

the IEEE802.3, IEEE802.3u, and IEEE802.3x

2k MAC address

specifications. The DSP approach is utilized for

384k bits packet buffer memory

designing transceivers with 0.18um technology; they

Support auto-polarity for 10Mbps

have high noise immunity and robust performance.

Filter/ forward reserved address option

Broadcast storm protection

IP175C/IP175CH operates in store and forward

Auto MDI-MDIX

mode. It supports flow control, auto MDI/MDI-X,

Support three MII/RMII ports

CoS, port base VLAN, bandwidth control, DiffServ,

Support SMI with MDC up to 12.5 Mhz

SMART MAC and LED functions, etc. Each port can

Support tagging & un-tagging

be configured to auto-negotiation or forced

Support Port base VLAN & tag VLAN

10M/100M, full/half duplexmode. Using an

Support CoS

EEPROM or pull up/down resistors on specified pins

Support port security option

can configure the desired options.

Support SMART MAC function

Support spanning tree protocol

Besides

5-port

switch

application,

Max packet length 1552/ 1536 bytes

IP175C/IP175CH supports three MII/RMII ports for

Support 8-level bandwidth control

router application, which supports 4 LAN ports, one

Support Link quality LED for 100Mbps

WAN port and one HOME/PNA or Access point. The

Support direct, serial and dual color mode LED external MAC can monitor or configure

Support one fiber port with far end fault function IP175C/IP175CH by accessing MII registers through

for

IP175CH

only

SMI0.

Built in linear regulator control circuit

Low power consumption

MII/RMII port also can be configured to be MAC

0.18um, 128-pin PQFP

mode. It is used to interface an external PHY to

Support Lead Free package (Please refer to the work as a 5+1 switch. Through SMI1

Order Information)

IP175C/IP175CH can monitor and configure

external PHY.

Note – some features need CPU support, please

refer to the detail description inside this data sheet

IP175CH

supports one fiber port with far end fault

function

1/111

Mar 09, 2007

IP175C/IP175CH-DS-R14

IP175C/IP175C LF/IP175CH/IP175CH LF

Data Sheet

Table Of Contents

Features................................................................................................................................................... 1

General Description................................................................................................................................. 1

Table Of Contents.................................................................................................................................... 2

Revision History....................................................................................................................................... 4

Comparison Table of IP175A & IP175C/IP175CH................................................................................... 6

Pin diagram (IP175C) .............................................................................................................................. 7

Pin diagram (IP175CH) ........................................................................................................................... 8

1 Pin description................................................................................................................................ 12

2 Functional Description.................................................................................................................... 34

Flow control........................................................................................................................ 34

2.1

Broadcast storm protection ................................................................................................ 34

2.2

Port locking (Port security)................................................................................................. 34

2.3

Port base VLAN ................................................................................................................. 34

2.4

Tag VLAN / Tag and un-tag function .................................................................................. 35

2.5

Tag and un-tag function ........................................................................................ 35

2.5.1

Tag VLAN .............................................................................................................. 35

2.5.2

Tag/ un-tag function and Tag VLAN function in a router application..................... 35

2.5.3

MII/RMII.............................................................................................................................. 36

2.6

SMART MAC...................................................................................................................... 42

2.7

System configuration ............................................................................................ 42

2.7.1

Packet from LAN to WAN ..................................................................................... 44

2.7.2

Packet from WAN to LAN ..................................................................................... 44

2.7.3

Built in regulator ................................................................................................................. 45

2.8

CoS .................................................................................................................................... 46

2.9

Port base priority................................................................................................... 46

2.9.1

Frame base priority ............................................................................................... 46

2.9.2

2.10 Spanning tree ..................................................................................................................... 48

Port states ............................................................................................................. 48

2.10.1

Special tag.......................................................................................................................... 49

2.11

From CPU to switch .............................................................................................. 49

2.11.1

From switch to CPU .............................................................................................. 49

2.11.2

2.12 Static MAC address table................................................................................................... 50

2.13 Serial mode LED................................................................................................................ 51

2.14 LED Blink Timing................................................................................................................ 53

2.15 Serial management interface ............................................................................................. 54

2.16 Force mode of PHY ........................................................................................................... 56

2.17 Reset.................................................................................................................................. 56

2.18 Bandwidth control............................................................................................................... 56

2.19 Fiber mode of port 4 (for IP175CH only)............................................................................ 56

2.20 MII registers of PHY........................................................................................................... 58

2.21 MII registers of Switch controller........................................................................................ 66

3 Electrical Characteristics .............................................................................................................. 101

Absolute Maximum Rating ............................................................................................... 101

3.1

DC Characteristic............................................................................................................. 101

3.2

AC Timing......................................................................................................................... 102

3.3

Reset Timing ....................................................................................................... 102

3.3.1

PHY Mode MII Timing ......................................................................................... 102

3.3.2

MAC Mode MII Timing ........................................................................................ 104

3.3.3

RMII Timing......................................................................................................... 105

3.3.4

SNI Timing .......................................................................................................... 106

3.3.5

SMI Timing .......................................................................................................... 107

3.3.6

2/111

Mar 09, 2007

IP175C/IP175CH-DS-R14

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