IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
5 Port 10/100 Ethernet Integrated Switch
Features
General Description
IP175A PCB compatible (pins compatible)
IP175C/IP175CH integrates a 6-port switch
Built in 6 MAC and 5 PHY
controller, SSRAM, and 5 10/100 Ethernet
Each port can be configured to be 10Base-T, transceivers. Each of the transceivers complies with
100Base-TX
the IEEE802.3, IEEE802.3u, and IEEE802.3x
2k MAC address
specifications. The DSP approach is utilized for
384k bits packet buffer memory
designing transceivers with 0.18um technology; they
Support auto-polarity for 10Mbps
have high noise immunity and robust performance.
Filter/ forward reserved address option
Broadcast storm protection
IP175C/IP175CH operates in store and forward
Auto MDI-MDIX
mode. It supports flow control, auto MDI/MDI-X,
Support three MII/RMII ports
CoS, port base VLAN, bandwidth control, DiffServ,
Support SMI with MDC up to 12.5 Mhz
SMART MAC and LED functions, etc. Each port can
Support tagging & un-tagging
be configured to auto-negotiation or forced
Support Port base VLAN & tag VLAN
10M/100M, full/half duplexmode. Using an
Support CoS
EEPROM or pull up/down resistors on specified pins
Support port security option
can configure the desired options.
Support SMART MAC function
Support spanning tree protocol
Besides
a
5-port
switch
application,
Max packet length 1552/ 1536 bytes
IP175C/IP175CH supports three MII/RMII ports for
Support 8-level bandwidth control
router application, which supports 4 LAN ports, one
Support Link quality LED for 100Mbps
WAN port and one HOME/PNA or Access point. The
Support direct, serial and dual color mode LED external MAC can monitor or configure
Support one fiber port with far end fault function IP175C/IP175CH by accessing MII registers through
for
IP175CH
only
SMI0.
Built in linear regulator control circuit
Low power consumption
MII/RMII port also can be configured to be MAC
0.18um, 128-pin PQFP
mode. It is used to interface an external PHY to
Support Lead Free package (Please refer to the work as a 5+1 switch. Through SMI1
Order Information)
IP175C/IP175CH can monitor and configure
external PHY.
Note – some features need CPU support, please
refer to the detail description inside this data sheet
IP175CH
supports one fiber port with far end fault
function
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Copyright © 2004, IC Plus Corp.
Mar 09, 2007
IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
Table Of Contents
Features................................................................................................................................................... 1
General Description................................................................................................................................. 1
Table Of Contents.................................................................................................................................... 2
Revision History....................................................................................................................................... 4
Comparison Table of IP175A & IP175C/IP175CH................................................................................... 6
Pin diagram (IP175C) .............................................................................................................................. 7
Pin diagram (IP175CH) ........................................................................................................................... 8
1 Pin description................................................................................................................................ 12
2 Functional Description.................................................................................................................... 34
Flow control........................................................................................................................ 34
2.1
Broadcast storm protection ................................................................................................ 34
2.2
Port locking (Port security)................................................................................................. 34
2.3
Port base VLAN ................................................................................................................. 34
2.4
Tag VLAN / Tag and un-tag function .................................................................................. 35
2.5
Tag and un-tag function ........................................................................................ 35
2.5.1
Tag VLAN .............................................................................................................. 35
2.5.2
Tag/ un-tag function and Tag VLAN function in a router application..................... 35
2.5.3
MII/RMII.............................................................................................................................. 36
2.6
SMART MAC...................................................................................................................... 42
2.7
System configuration ............................................................................................ 42
2.7.1
Packet from LAN to WAN ..................................................................................... 44
2.7.2
Packet from WAN to LAN ..................................................................................... 44
2.7.3
Built in regulator ................................................................................................................. 45
2.8
CoS .................................................................................................................................... 46
2.9
Port base priority................................................................................................... 46
2.9.1
Frame base priority ............................................................................................... 46
2.9.2
2.10 Spanning tree ..................................................................................................................... 48
Port states ............................................................................................................. 48
2.10.1
Special tag.......................................................................................................................... 49
2.11
From CPU to switch .............................................................................................. 49
2.11.1
From switch to CPU .............................................................................................. 49
2.11.2
2.12 Static MAC address table................................................................................................... 50
2.13 Serial mode LED................................................................................................................ 51
2.14 LED Blink Timing................................................................................................................ 53
2.15 Serial management interface ............................................................................................. 54
2.16 Force mode of PHY ........................................................................................................... 56
2.17 Reset.................................................................................................................................. 56
2.18 Bandwidth control............................................................................................................... 56
2.19 Fiber mode of port 4 (for IP175CH only)............................................................................ 56
2.20 MII registers of PHY........................................................................................................... 58
2.21 MII registers of Switch controller........................................................................................ 66
3 Electrical Characteristics .............................................................................................................. 101
Absolute Maximum Rating ............................................................................................... 101
3.1
DC Characteristic............................................................................................................. 101
3.2
AC Timing......................................................................................................................... 102
3.3
Reset Timing ....................................................................................................... 102
3.3.1
PHY Mode MII Timing ......................................................................................... 102
3.3.2
MAC Mode MII Timing ........................................................................................ 104
3.3.3
RMII Timing......................................................................................................... 105
3.3.4
SNI Timing .......................................................................................................... 106
3.3.5
SMI Timing .......................................................................................................... 107
3.3.6
U
2/111
Copyright © 2004, IC Plus Corp.
Mar 09, 2007
IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
3.3.7
EEPROM Timing................................................................................................. 109
Thermal Data ................................................................................................................... 109
3.4
Order Information ..........................................................................................................................110
Package Detail .............................................................................................................................. 111
4
5
3/111
Copyright © 2004, IC Plus Corp.
Mar 09, 2007
IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
Revision History
Revision #
IP175C-API-R01
IP175C-DS-R01
Change Description
Advanced Product Information.
1. Initial release.
2. The difference between IP175C-API-R01 & IP175C-DS-R01
2-1. Remove SCA.
2-2. RMII clock output pin changed.
2-3. Pin 116: CLK_SEL
REG_HIGH
1. Modify RMII1 Pin description.
2. MII Register not compatible to IP175A.
3. Add comparison table of IP175A & IP175C.
1. Update page 28 Pin description of X1
2. Add page 99~105
3. Remove POA
4. Remove MII registers PHY 5 and PHY 6
1. Change MDC1 from Pin 53 to Pin 113
2. Add the description of MII0_RXCLK and MII0_TXCLK are in phase.
3. Modify the description of bandwidth control Register.
4. REG_HIGH is internally bounded to GND for the linear regulator to generate a 1.8v
voltage source.
1. Modify the value of bit [9:4] of register 4 of PHY 0 ~ PHY 4 from 6’h05 to 6’h18.
2. Add REGOUT to DC charasteritic table.
1. Add Bandwidth control description.
2. Update REGOUT voltage from 1.8v (±5%) to 1.82v (±6%)
1. Add port security in page 31
2. Add notice for different configuration in router application in page 7
3. Add notice for different configuration in Smart Mac application in page 39
4. Change register setting for 30.1[5:0] from 6’h3f to 6’h30 in page 40
5. Change REGOUT voltage from 1.82v (±6%) to 1.70v ~ 1.93v in page 42
6. Modify VIH, VIL in page 97
7. Add reset timing in page 98
8. Change REGOUT voltage from 1.82v (±6%) to 1.70v ~ 1.93v in page 9
9. Change band gap resister from 6.2K to 6.19K in page 27
10. Change led_sel [1:0] from {1,0} to {0,1} in page 30
11. Add AVCC & VCC pin list in page 30
1. Remove speed up column in page 49
2. Add in Thermal Data in page 105
3. PHY 30 MII register 12 bit [1] change from * to 1’b1 in page 84
1. Add phy_30_reg_12[8] (bw_en_qm) in page 84
2. Add Note on page 1 for CPU
1. Add the order information for lead free package
1. Change REGOUT voltage upper limit from 1.93v to 2.00v on page 10, 43, 98
2. Change VCC upper limit to 2.00 on page 98
3. Add “All ports link at 10Mbps mode” to REG_OUT Conditions on page 98
IP175C-DS-R02
IP175C-DS-R03
IP175C-DS-R04
IP175C-DS-R05
IP175C-DS-R06
IP175C-DS-R07
IP175C-DS-R08
IP175C-DS-R09
IP175C-DS-R10
IP175C-DS-R11
4/111
Copyright © 2004, IC Plus Corp.
Mar 09, 2007
IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
Revision History
Revision #
IP175C-DS-R12
1.
2.
3.
4.
5.
6.
7.
8.
Change Description
Change to EEPROM register 14~18 or MII register 19~21 on page 32
Add SERIAL_LED_MODE to Pin diagram on page 6
Add pin 112 description for SERIAL_LED_MODE on page 27
Add PHY_31_REG_5[1] SERIAL_LED_MODE on page 97
Add SERIAL_LED_MODE = 0 on page 50
Add description for SERIAL_LED_MODE selection on page 50
Change MII0 MAC mode PHY address to 00000 on page 36
Change P4_FORCE_100 from 22.4 to 20.4 on page 36
IP175Cx-DS-R13
IP175Cx-DS-R14
1. Replace IP175C with
IP175C/IP175CH
2. Add “IP175CH support one fiber “ to feature list and general description on page
1
3. Modify Comparison Table on page 6 for IP175CH only
4. Add IP175CH Pin diagram on page 8
5. Add FXSD4 Pin description on page 30
6. Add “Fiber mode of port 4 (for IP175CH only)” function description on page 56
7. Modify Order Information on page 111
8. Add Fiber I/O Electrical Characteristics on page 102
1. Modify flow control description on page 34
2. Modify IPL/IPH description on page 12
3. Modify Dual color mode LED Link off status value on page 33
4. Add X1 VIL & X1 VIH on page 102
5. Add 384k bits packet buffer memory on page 1
5/111
Copyright © 2004, IC Plus Corp.
Mar 09, 2007
IP175C/IP175CH-DS-R14
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