IS25LP032A-JMLA2 datasheet, PDF

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IS25LP032A-JMLA2: DescriptionFlash, 32MX1, PDSO16, 0.300 INCH, ROHS COMPLIANT, PLASTIC, SOIC-16; Categorystorage storage; File Size2MB，99 Pages; ManufacturerIntegrated Silicon Solution ( ISSI )

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IS25LP032A-JMLA2 Overview

Flash, 32MX1, PDSO16, 0.300 INCH, ROHS COMPLIANT, PLASTIC, SOIC-16

IS25LP032A-JMLA2 Parametric

Parameter Name	Attribute value
Maker	Integrated Silicon Solution ( ISSI )
package instruction	SOP,
Reach Compliance Code	unknow
ECCN code	EAR99
Maximum clock frequency (fCLK)	133 MHz
JESD-30 code	R-PDSO-G16
length	10.3 mm
memory density	33554432 bi
Memory IC Type	FLASH
memory width	1
Number of functions	1
Number of terminals	16
word count	33554432 words
character code	32000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	105 °C
Minimum operating temperature	-40 °C
organize	32MX1
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	SERIAL
Programming voltage	3 V
Filter level	AEC-Q100
Maximum seat height	2.65 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
type	NOR TYPE
width	7.5 mm

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IS25LP064A

IS25LP032A

64/32Mb

3V SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI & QUAD

I/O QPI DTR INTERFACE

DATA SHEET

IS25LP064A/032A

GENERAL DESCRIPTION

The IS25LP064A/032A Serial Flash memory offers a versatile storage solution with high flexibility and

performance in a simplified pin count package. ISSI’s “Industry Standard Serial Interface” Flash are for systems

that require limited space, a low pin count, and low power consumption. The device is accessed through a 4-

wire SPI Interface consisting of a Serial Data Input (SI), Serial Data Output (SO), Serial Clock (SCK), and Chip

Enable (CE#) pins, which can also be configured to serve as multi-I/O (see pin descriptions).

The device supports Dual and Quad I/O as well as standard, Dual Output, and Quad Output SPI. Clock

frequencies of up to 133MHz allow for equivalent clock rates of up to 532MHz (133MHz x 4) which equates to

66Mbytes/s of data throughput. The IS25xP series of Flash adds support for DTR (Double Transfer Rate)

commands that transfer addresses and read data on both edges of the clock. These transfer rates can

outperform 16-bit Parallel Flash memories allowing for efficient memory access to support XIP (execute in

place) operation.

The memory array is organized into programmable pages of 256-bytes. This family supports page program

mode where 1 to 256 bytes of data are programmed in a single command. QPI (Quad Peripheral Interface)

supports 2-cycle instruction further reducing instruction times. Pages can be erased in groups of 4Kbyte

sectors, 32Kbyte blocks, 64Kbyte blocks, and/or the entire chip. The uniform sector and block architecture

allows for a high degree of flexibility so that the device can be utilized for a broad variety of applications

requiring solid data retention.

GLOSSARY

Standard SPI

In this operation, a 4-wire SPI Interface is utilized, consisting of Serial Data Input (SI), Serial Data Output (SO),

Serial Clock (SCK), and Chip Enable (CE#) pins. Instructions are sent via the SI pin to encode instructions,

addresses, or input data to the device on the rising edge of SCK. The SO pin is used to read data or to check the

status of the device. This device supports SPI bus operation modes (0,0) and (1,1).

Multi I/O SPI

Multi-I/O operation utilizes an enhanced SPI protocol to allow the device to function with Dual Output, Dual Input

and Output, Quad Output, and Quad Input and Output capability. Executing these instructions through SPI

mode will achieve double or quadruple the transfer bandwidth for READ and PROGRAM operations.

QPI

The device supports Quad Peripheral Interface (QPI) operations only when the device is switched from

Standard/Dual/Quad SPI mode to QPI mode using the enter QPI (35h) instruction. The typical SPI protocol

requires that the byte-long instruction code being shifted into the device only via SI pin in eight serial clocks. The

QPI mode utilizes all four I/O pins to input the instruction code thus requiring only two serial clocks. This can

significantly reduce the SPI instruction overhead and improve system performance. Only QPI mode or

SPI/Dual/Quad mode can be active at any given time. Enter QPI (35h) and Exit QPI (F5h) instructions are used

to switch between these two modes, regardless of the non-volatile Quad Enable (QE) bit status in the Status

SO pins become bidirectional I/O0 and I/O1, and WP# and HOLD# pins become I/O2 and I/O3 respectively

during QPI mode.

DTR

In addition to SPI and QPI features, the device also supports Fast READ DTR operation, which allows high data

throughput while running at lower clock frequencies. DTR READ mode uses both rising and falling edges of the

clock to drive output, resulting in reducing input and output cycles by half.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

11/06/2015

IS25LP064A/032A

TABLE OF CONTENTS

FEATURES .......................................................................................................................................................... 2

GENERAL DESCRIPTION .................................................................................................................................. 3

TABLE OF CONTENTS ....................................................................................................................................... 4

PIN CONFIGURATION ................................................................................................................................. 7

PIN DESCRIPTIONS .................................................................................................................................... 9

BLOCK DIAGRAM ...................................................................................................................................... 11

SPI MODES DESCRIPTION ...................................................................................................................... 12

SYSTEM CONFIGURATION ...................................................................................................................... 14

5.1 BLOCK/SECTOR ADDRESSES .......................................................................................................... 14

REGISTERS ............................................................................................................................................... 15

6.1 STATUS REGISTER ............................................................................................................................ 15

6.2 FUNCTION REGISTER ........................................................................................................................ 18

6.3 READ REGISTER................................................................................................................................. 19

PROTECTION MODE................................................................................................................................. 21

7.1 HARDWARE WRITE PROTECTION.................................................................................................... 21

7.2 SOFTWARE WRITE PROTECTION .................................................................................................... 21

DEVICE OPERATION ................................................................................................................................ 22

8.1 NORMAL READ OPERATION (NORD, 03h) ....................................................................................... 24

8.2 FAST READ OPERATION (FRD, 0Bh) ................................................................................................ 26

8.3 HOLD OPERATION .............................................................................................................................. 28

8.4 FAST READ DUAL I/O OPERATION (FRDIO, BBh) ........................................................................... 28

8.5 FAST READ DUAL OUTPUT OPERATION (FRDO, 3Bh) ................................................................... 31

8.6 FAST READ QUAD OUTPUT OPERATION (FRQO, 6Bh).................................................................. 32

8.7 FAST READ QUAD I/O OPERATION (FRQIO, EBh) .......................................................................... 34

8.8 PAGE PROGRAM OPERATION (PP, 02h) .......................................................................................... 38

8.9 QUAD INPUT PAGE PROGRAM OPERATION (PPQ, 32h/38h) ........................................................ 40

8.10 ERASE OPERATION ......................................................................................................................... 41

8.11 SECTOR ERASE OPERATION (SER, D7h/20h) ............................................................................... 42

8.12 BLOCK ERASE OPERATION (BER32K:52h, BER64K:D8h) ............................................................ 43

8.13 CHIP ERASE OPERATION (CER, C7h/60h) ..................................................................................... 45

8.14 WRITE ENABLE OPERATION (WREN, 06h) .................................................................................... 46

8.15 WRITE DISABLE OPERATION (WRDI, 04h) ..................................................................................... 47

8.16 READ STATUS REGISTER OPERATION (RDSR, 05h) ................................................................... 48

8.17 WRITE STATUS REGISTER OPERATION (WRSR, 01h) ................................................................. 49

8.18 READ FUNCTION REGISTER OPERATION (RDFR, 48h) ............................................................... 50

8.19 WRITE FUNCTION REGISTER OPERATION (WRFR, 42h)............................................................. 51

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

11/06/2015

IS25LP064A/032A

8.20 ENTER QUAD PERIPHERAL INTERFACE (QPI) MODE OPERATION (QPIEN, 35h; QPIDI, F5h) 52

8.21 PROGRAM/ERASE SUSPEND & RESUME ...................................................................................... 53

8.22 ENTER DEEP POWER DOWN (DP, B9h) ......................................................................................... 55

8.23 RELEASE DEEP POWER DOWN (RDPD, ABh) ............................................................................... 56

8.24 SET READ PARAMETERS OPERATION (SRP, C0h) ...................................................................... 57

8.25 READ PRODUCT IDENTIFICATION (RDID, ABh) ............................................................................ 59

8.26 READ PRODUCT IDENTIFICATION BY JEDEC ID OPERATION (RDJDID, 9Fh; RDJDIDQ, AFh) 61

8.27 READ DEVICE MANUFACTURER AND DEVICE ID OPERATION (RDMDID, 90h) ........................ 62

8.28 READ UNIQUE ID NUMBER (RDUID, 4Bh) ...................................................................................... 63

8.29 READ SFDP OPERATION (RDSFDP, 5Ah) ...................................................................................... 64

8.30 NO OPERATION (NOP, 00h) ............................................................................................................. 64

8.31 SOFTWARE RESET (RESET-ENABLE (RSTEN, 66h) AND RESET (RST, 99h)) AND HARDWARE

RESET ........................................................................................................................................................ 65

8.32 SECURITY INFORMATION ROW ...................................................................................................... 66

8.33 INFORMATION ROW ERASE OPERATION (IRER, 64h) ................................................................. 67

8.34 INFORMATION ROW PROGRAM OPERATION (IRP, 62h) ............................................................. 68

8.35 INFORMATION ROW READ OPERATION (IRRD, 68h) ................................................................... 69

8.36 FAST READ DTR MODE OPERATION (FRDTR, 0Dh) ..................................................................... 70

8.37 FAST READ DUAL IO DTR MODE OPERATION (FRDDTR, BDh) .................................................. 72

8.38 FAST READ QUAD IO DTR MODE OPERATION (FRQDTR, EDh) ................................................. 75

8.39 SECTOR LOCK/UNLOCK FUNCTIONS ............................................................................................ 79

ELECTRICAL CHARACTERISTICS........................................................................................................... 81

9.1 ABSOLUTE MAXIMUM RATINGS

(1)

................................................................................................... 81

9.2 OPERATING RANGE ........................................................................................................................... 81

9.3 DC CHARACTERISTICS ...................................................................................................................... 82

9.4 AC MEASUREMENT CONDITIONS .................................................................................................... 83

9.5 PIN CAPACITANCE ............................................................................................................................. 83

9.6 AC CHARACTERISTICS ...................................................................................................................... 84

9.7 SERIAL INPUT/OUTPUT TIMING ........................................................................................................ 86

9.8 POWER-UP AND POWER-DOWN ...................................................................................................... 88

9.9 PROGRAM/ERASE PERFORMANCE ................................................................................................. 89

9.10 RELIABILITY CHARACTERISTICS ................................................................................................... 89

10.

PACKAGE TYPE INFORMATION ......................................................................................................... 90

10.1 8-Pin JEDEC 208mil Broad Small Outline Integrated Circuit (SOIC) Package (B) ............................ 90

10.2 8-Contact Ultra-Thin Small Outline No-Lead (WSON) Package 6x5mm (K)...................................... 91

10.3 8-Contact Ultra-Thin Small Outline No-Lead (WSON) Package 8x6mm (L) ...................................... 92

10.4 8-Pin 208mil VSOP Package (F) ........................................................................................................ 93

10.5 16-lead Plastic Small Outline package (300 mils body width) (M) ..................................................... 94

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

11/06/2015

IS25LP032A-JMLA2 Related Products

	IS25LP032A-JMLA2	IS25LP064A-JBLE1	IS25LP064A-JBLA2	IS25LP064A-DGLA3
Description	Flash, 32MX1, PDSO16, 0.300 INCH, ROHS COMPLIANT, PLASTIC, SOIC-16	Flash, 64MX1, PDSO8, 0.208 INCH, ROHS COMPLIANT, SOIC-8	Flash, 64MX1, PDSO8, 0.208 INCH, ROHS COMPLIANT, SOIC-8	Flash, 8MX8, PBGA24, TFBGA-24
package instruction	SOP,	SOP,	SOP,	TBGA,
Reach Compliance Code	unknow	unknown	unknown	unknown
Maximum clock frequency (fCLK)	133 MHz	133 MHz	133 MHz	133 MHz
JESD-30 code	R-PDSO-G16	S-PDSO-G8	S-PDSO-G8	R-PBGA-B24
length	10.3 mm	5.28 mm	5.28 mm	8 mm
memory density	33554432 bi	67108864 bit	67108864 bit	67108864 bit
Memory IC Type	FLASH	FLASH	FLASH	FLASH
memory width	1	1	1	8
Number of functions	1	1	1	1
Number of terminals	16	8	8	24
word count	33554432 words	67108864 words	67108864 words	8388608 words
character code	32000000	64000000	64000000	8000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	105 °C	125 °C	105 °C	125 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C
organize	32MX1	64MX1	64MX1	8MX8
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	SOP	SOP	TBGA
Package shape	RECTANGULAR	SQUARE	SQUARE	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	GRID ARRAY, THIN PROFILE
Parallel/Serial	SERIAL	SERIAL	SERIAL	SERIAL
Programming voltage	3 V	3 V	3 V	3 V
Maximum seat height	2.65 mm	2.16 mm	2.16 mm	1.2 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	2.3 V	2.3 V	2.3 V	2.3 V
Nominal supply voltage (Vsup)	3 V	3 V	3 V	3 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	AUTOMOTIVE	INDUSTRIAL	AUTOMOTIVE
Terminal form	GULL WING	GULL WING	GULL WING	BALL
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	1 mm
Terminal location	DUAL	DUAL	DUAL	BOTTOM
width	7.5 mm	5.28 mm	5.28 mm	6 mm
Filter level	AEC-Q100	-	AEC-Q100	AEC-Q100

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