Integrated
Circuit
Systems, Inc.
Preliminary Information
M2004-x2
*
F
REQUENCY
T
RANSLATION
PLL F
AMILY
P
IN
A
SSIGNMENT
(9 x 9 mm SMT)
M0
GND
REF_CLK
DIF_REF
nDIF_REF
REF_SEL
NC
NC
VCC
M1
M2
M3
M4
M5
VCC
DNC
DNC
DNC
27
26
25
24
23
22
21
20
19
G
ENERAL
D
ESCRIPTION
The M2004 variants -22, -32, -42, and -52 are VCSO
(Voltage Controlled SAW Oscillator)
based clock generator PLLs
designed for clock frequency
translation and jitter attenuation in
a high-speed data communications
system. The clock multiplication
ratio and output divider ratio are
pin selectable. External loop components allow the
tailoring of PLL loop response. Based on the M2004-02,
these device variants add the Hitless Switching with
Phase Build-out (HS/PBO) feature. HS/PBO ensures
that reference clock reselection does not disrupt the
output clock. In addition, a fixed Narrow Loop
Bandwidth feature (Fixed NBW) is included in the some
of the device variants.
28
29
30
31
32
33
34
35
36
M2004-x2
(Top View)
18
17
16
15
14
13
12
11
10
NC
MR
nFOUT
FOUT
GND
N1
N0
VCC
GND
F
EATURES
◆
Pin-compatible with M2004-02/-12, these new product
variants offer new functions
◆
Hitless Switching with Phase Build-out to ensure
SONET/SDH MTIE and TDEV compliance during
reference clock reselection
◆
Fixed Narrow Loop Bandwidth feature available
◆
Ideal for OC-48/192 data clock
◆
Integrated SAW (surface acoustic wave) delay line
◆
VCSO frequency from 300 to 700MHz
**
◆
Low phase jitter of < 0.5ps rms, typical
(12kHz to 20MHz or 50kHz to 80MHz)
◆
Pin-selectable configuration
◆
Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
◆
Industrial temperature available
◆
Single 3.3V power supply
◆
Small 9 x 9 mm SMT (surface mount) package
Figure 1: Pin Assignment
Example Input / Output Frequency Combinations
Input (MHz) VCSO ** (MHz) Output (MHz)
19.44
77.76
622.08
77.76
311.04
155.52
622.08
Application
OC-12 / 48
/192
Table 1: Example Input / Output Frequency Combinations
Device Variants and Corresponding Functions
Hitless Switching /
Phase Build-out Triggered by
Phase Transient Mux Reselection
M2004-02
no
no
M2004-12
✓
Yes
✓
Yes
M2004-22
no
no
M2004-32
✓
Yes
✓
Yes
M2004-42
no
✓
Yes
M2004-52
no
✓
Yes
Variant
Fixed
NBW
no
no
✓
Yes
✓
Yes
no
✓
Yes
Table 2: Device Variants and Corresponding Functions
* This sheet covers only parts numbered M2004-22, -32, -42, -52.
See M2004-02/-12 Product Data Sheet
for M2004-02 & M2004-12.
** Specify VCSO center frequency at time of order.
S
IMPLIFIED
B
LOCK
D
IAGRAM
M2004-x2
DIF_REF
nDIF_REF
REF_CLK
REF_SEL
M Divider
N Divider
6
M5:0
2
N1:0
FOUT
nFOUT
0
1
Loop
Filter
VCSO
Figure 2: Simplified Block Diagram
M2004-x2 Datasheet Rev 1.3
M2004-x2 Frequency Translation PLL Family
GND
GND
GND
OP_IN
nOP_OUT
nVC
VC
OP_OUT
nOP_IN
1
2
3
4
5
6
7
8
9
MR
Revised 10Sep2003
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Circuit
Systems, Inc.
M2004-
X
2
F
REQUENCY
T
RANSLATION
PLL F
AMILY
Preliminary Information
P
IN
D
ESCRIPTIONS
Number
1, 2, 3, 10, 14, 26
4
9
5
8
6
7
11, 19, 33
12
13
15
16
Name
GND
OP_IN
nOP_IN
nOP_OUT
OP_OUT
nVC
VC
VCC
N0
N1
FOUT
nFOUT
I/O
Configuration
Description
Ground
Input
Output
Input
Power
Input
Output
Power supply ground connections.
External loop filter connections. See Figure 4,
External Loop Filter, on pg. 5.
Power supply connection, connect to +
3.3
V.
N divider (output divider) inputs
N1
:
N0
.
Internal pull-down resistor
1
LVCMOS/LVTTL. See Table 6, N Divider Pin
Selection
,
on pg. 3.
No internal terminator
Clock output pair. Differential LVPECL.
17
MR
Input
Reset:
Logic
1
resets M and N dividers and forces
1
Internal pull-down resistor
FOUT
to LOW and
nFOUT
to HIGH.
Logic
0
enables the outputs.
LVCMOS/LVTTL.
No connection.
Internal pull-down resistor
1
Internal pull-UP resistor
1
Reference clock input selection. LVCMOS/LVTTL.
See Table 4, Reference Clock Input Selection, on
pg. 3.
REF_SEL
triggers Hitless Switching (HS/PBO)
when toggled.
18
20
21
22
23
24
25
27
28
29
30
31
32
34, 35, 36
NC
NC
NC
REF_SEL
nDIF_REF
DIF_REF
REF_CLK
M0
M1
M2
M3
M4
M5
DNC
Input
Input
Input
Reference clock input pair.
Internal pull-down resistor
1
Differential LVPECL or LVDS.
Internal pull-down resistor
1
Reference clock input. LVCMOS/LVTTL.
Input
Internal pull-down resistor
1
M divider (feedback divider) inputs
M5
:
M0
.
See Table 5, M Divider Pin Selection, on pg. 3.
Internal pull-UP resistor
1
Do Not Connect.
Table 3: Pin Descriptions
Note 1: For typical values of internal pull-down and pull-up resistors, see
DC Characteristics
on pg. 7.
M2004-x2 Datasheet Rev 1.3
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Circuit
Systems, Inc.
M2004-
X
2
F
REQUENCY
T
RANSLATION
PLL F
AMILY
Preliminary Information
D
ETAILED
B
LOCK
D
IAGRAM
R
LOOP
C
LOOP
R
POST
C
POST
C
POST
R
LOOP
C
LOOP
OP_OUT
R
POST
nOP_OUT
nVC
VC
External
Loop Filter
Components
M2004-x2
DIF_REF
nDIF_REF
REF_CLK
REF_SEL
MUX
Phase
Detector
OP_IN
nOP_IN
R
IN
SAW Delay Line
0
1
R
IN
Loop Filter
Amplifier
Phase
Shifter
VCSO
M Divider
M = 3-63
N Divider
N = 1,2,4,8
FOUT
nFOUT
Pin Configuration Register
6
2
M5:0
N1:0
MR
Figure 3: Detailed Block Diagram
PLL D
IVIDER
S
ELECTION
T
ABLES
Reference Clock Input Selection
REF_SEL
Pin Setting
(Pin 22)
0
1
Reference Input Selection
DIF_REF, nDIF_REF
REF_CLK
Table 4: Reference Clock Input Selection
N Divider Pin Selection
N1:0 Settings N Divider
(Pin 13 and 12) Value
N1
N0
0
0
1
0
1
2
1
0
4
1
1
8
Sample
Output
Frequency (MHz)
1
(FOUT, nFOUT)
622.08
311.04
155.52
77.76
Table 6: N Divider Pin Selection
M Divider Pin Selection
M5:0
Pin
Settings
(Pins 32 - 27)
M5
-
M0
Definition
Sample Input Clock
Freq (MHz)
F
VCSO
= F
VCSO
=
622.08
1
,
625.00
2
Note 1: F
VCSO
= 622.08MHz (e.g., M2004-22-622.0800)
5
3
4 3 2 1 0
Feedback Divider Value “M”
0 00011
M =
3
minimum
0 00100
M=4
.
.
.
.
.
.
.
.
.
.
.
.
.
.
155.52
77.76
38.80
156.25
0 01000
0 10000
0 1 1 0 0
.
1
1 00000
1 11111
M=
8
M =
16
M =
25
M =
32
M =
63
25.00
19.44
Table 5: M Divider Pin Selection
Note 1: F
VCSO
= 622.08 MHz (e.g., M2004-22-622.0800)
Note 2: F
VCSO
= 625.00 MHz (e.g., M2004-22-625.0000)
Note 3: M5 pin has a pull-up resister; M4-M0, pull-down.
M2004-x2 Datasheet Rev 1.3
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3 of 10
Communications Modules
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Revised 10Sep2003
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Systems, Inc.
M2004-
X
2
F
REQUENCY
T
RANSLATION
PLL F
AMILY
Preliminary Information
Input Reference Clocks
An internal input MUX is provided for input reference
clock selection. One input reference clock is selected
from between a single-ended LVCMOS / LVTTL clock
input or a differential LVPECL or LVDS clock input pair.
The maximum input frequency is 175MHz.
PLL Operation
The M2004-x2 is a complete clock PLL. It uses a phase
detector and configurable dividers to synchronize the
output of the VCSO with the selected reference clock.
The “M Divider” divides the VCSO output frequency,
feeding the result into the phase detector. The selected
input reference clock is fed into the other input of the
phase detector. The phase detector compares its two
inputs. It then causes the VCSO to increase or
decrease in speed as needed to phase- and frequency-
lock the VCSO to the reference input.
The value of M directly affects closed loop bandwidth.
F
UNCTIONAL
D
ESCRIPTION
The M2004-x2 is a PLL (Phase Locked Loop) based
clock generator that generates output clocks
synchronized to one of two selectable input reference
clocks. An internal high “Q” SAW delay line provides a
low jitter clock signal.
The device can be pin-configured for feedback divider
and output divider values. Output is LVPECL
compatible. External loop filter component values set
the PLL bandwidth to optimize jitter attenuation
characteristics.
The M2004-x2 is ideal for clock jitter attenuation and
frequency translation in 2.5 or 10 Gb optical network
line card applications.
Added Features and Device Variants
Hitless Switching with Phase Build-out (HS/PBO)
provides SONET/SDH MTIE and TDEV compliance
during a reference clock reselection when using the
internal mux (and also when using an external mux, in
two device variants).
A fixed Narrow Loop Bandwidth feature (Fixed NBW) is
included in some of the device variants.
All of the variants of the device are defined as follows:
•
The M2004-02 is the base variant (it omits both
HS/PBO and Fixed NBW).
•
The M2004-12 includes HS/PBO triggered by either a
phase transient or internal mux reselection.
•
The M2004-22 includes HS/PBO
−
triggered by
internal mux reselection only
−
and Fixed NBW.
•
The M2004-32 includes HS/PBO
−
triggered by either
a phase transient or internal mux reselection
−
and
Fixed NBW.
•
The M2004-42 includes HS/PBO triggered by internal
mux reselection only.
•
The M2004-52 includes HS/PBO
−
triggered by
internal mux reselection only
−
and Fixed NBW.
Device Variants and Corresponding Functions
Hitless Switching /
Phase Build-out Triggered by
Phase Transient Mux Reselection
no
no
Fixed
NBW
no
no
The M Divider
The relationship between the VCSO center frequency
(Fvcso), the M divider, and the input reference
frequency (Fref_clk) is:
Fvcso
=
Fref_clk
×
M
The product of M and the input frequency must be such
that it falls within the “lock” range of the VCSO.
See APR in AC Characteristics on pg. 8.
N Divider and Outputs
The M2004-x2 provides one differential LVPECL output
pair:
FOUT, nFOUT.
By using the N divider, the output
frequency can be the VCSO center frequency (Fvcso)
or 1/2, 1/4, or 1/8 Fvcso.
The
N1
and
N0
pins select the value for the N divider.
See Table 6, M Divider Pin Selection, on pg. 3.
Variant
M2004-02
M2004-12
M2004-22
M2004-32
M2004-42
M2004-52
When the N divider is included, the complete relation-
ship for the output frequency (Fout) is defined as:
M
Fvcso
Fout
=
-------------------
=
Fref_clk
×
--------
N
N
✓
Yes
no
✓
Yes
no
Configuration of M and N Dividers
The M and N dividers can be set by pin configuration
using the input pins
M0 - M5
,
N0
, and
N1
. The data on pins
M5:0
and pins
N1:0
is passed directly to the M and N
dividers.
The divider configuration of the M2004-x2 is reset when
the input pin
MR
is set HIGH.
MR
is set LOW for divider
configuration to be operational.
Revised 10Sep2003
●
✓
Yes
no
no
✓
Yes
✓
Yes
✓
Yes
✓
Yes
✓
Yes
no
✓
Yes
Table 7: Device Variants and Corresponding Functions
M2004-x2 Datasheet Rev 1.3
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Hitless Switching and Phase Build-out
A proprietary automatic Hitless Switching (HS) function
is included in the M2004-22, M2004-32, M2004-42, and
M2004-52. The HS function provides SONET/SDH
MTIE and TDEV compliance during a reference clock
reselection when using the internal mux. Two variants
are additionally triggered by reference clock reselection
when using an external mux (through detection of the
resulting phase transient).
*
A Phase Build-out (PBO)
function is also incorporated to absorb most of the
phase change in the reference clock input.
The combined HS/PBO function is armed after the
device locks to the input clock reference. Once armed,
HS/PBO is triggered according to device variant as
follows:
M2004-
X
2
F
REQUENCY
T
RANSLATION
PLL F
AMILY
Preliminary Information
External Loop Filter
To provide stable PLL operation, and thereby a low jitter
output clock, the M2004-x2 requires the use of an
external loop filter components. These are connected to
the provided filter pins (see Figure 4). Due to the
differential signal path design, the implementation
consists of two identical complementary RC filters as
shown in Figure 4, below.
R
LOOP
C
LOOP
R
POST
C
POST
C
POST
R
LOOP
OP_IN
4
9
C
LOOP
OP_OUT
8
5
R
POST
nOP_OUT
nVC
6
7
•
In the M2004-22, M2004-42 and M2004-52, HS/PBO
is only triggered by changing
REF_SEL
to switch the
input reference clock.
•
In the M2004-32, HS/PBO is triggered by either
reselection of the input mux or by detection at the
phase detector of an input phase transient beyond
4 ns.
Once triggered, the HS function narrows loop band-
width to control MTIE during locking to the new input
phase.
**
With proper configuration of the external loop
filter, the output clocks will comply with MTIE and TDEV
specifications for GR-253 (SONET) and ITU G.813
(SDH) during input reference clock changes.
The Phase Build-out (PBO) function enables the PLL to
absorb most of the phase change of the input clock.
The PBO function selects a new VCSO clock edge for
the phase detector feedback clock, selecting the edge
closest in phase to the new input clock phase. This
reduces re-lock time, the generation of wander, and
extra output clock cycles.
When the PLL locks to within 2 ns of the input clock
phase, the PLL returns to normal loop bandwidth and
the HS/PBO function is re-armed.
nOP_IN
VC
Figure 4: External Loop Filter
PLL bandwidth is affected by the “M” value as well as
the VCSO frequency. See Table 8, External Loop Filter
Component Values for M2004-42, on pg. 6.
In addition, loop bandwidth is affected by the Fixed
Narrow Loop Bandwidth (Fixed NBW) feature. See
Table 8, External Loop Filter Component Values for
M2004-42, on pg. 6.
Fixed Narrow Loop Bandwidth (Fixed NBW)
***
A fixed Narrow Loop Bandwidth feature (Fixed NBW) is
included in the M2004-22, M2004-32, and M2004-52.
These device variants have a narrower loop bandwidth
than the other variants. The internal resistor Rin is
2016 MΩ , increased from 16 kΩ . This lowers the loop
bandwidth by a factor of 125 (2 / 0.016) and lowers the
damping factor by a factor of 11.18 (the square root of
125), using the same loop components.
PLL Simulator Tool Available
A free PC software utility is available on the ICS website
(www.icst.com). The M2000 Timing Modules PLL
Simulator is a downloadable application that simulates
PLL jitter and wander transfer characteristics. This
enables the user to set appropriate external loop
component values in a given application.
*
Transient-triggered HS/PBO is not suitable for use with an
unstable reference clock that would induce phase jitter beyond
2 ns at the phase detector (e.g., Stratum DPLL clock sources and
unstable recovered network clocks intended for loop timing
configuration). Therefore, all of the HS/PBO devices offer the
internal mux-triggered HS/PBO capability.
** In the M2004-32 and M2004-52, the Fixed NBW function
permanently enables narrow bandwidth, therefore PBO is the
only actively-triggered function.
*** The M2004-02, M2004-12, and M2004-42 do not include
Fixed NBW.
M2004-x2 Datasheet Rev 1.3
Integrated Circuit Systems, Inc.
●
5 of 10
Communications Modules
●
Revised 10Sep2003
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