All Rights Reserved. No part of this document may be copied or reproduced in any form without the prior written permission of Discera, Inc. Discera Inc. may update or make
changes to the contents, products, programs or services described at any time without notice. This document neither states nor implies any kind of warranty, including, but not
limited to implied warranties of merchantability or fitness for a particular use.
Page 1 | 2010-3-16
DSC8124 Series
Item
Min.
-0.3
-0.3
-
-55
-
-
2.5 to 3.3V
PureSilicon™ Programmable HCSL Oscillator
Absolute Maximum Ratings
Max
Supply Voltage
Input Voltage
Junction Temp
Storage Temp
Soldering Temp
ESD
HBM
MM
CDM
+4.0
VDD+0.3
+150
+150
+260
4000
400
1500
Unit
V
V
°C
°C
°C
V
Condition
Ordering Code
DSC8124
Family
CE1
-
100.0000
T
40 sec max.
Package, Temp
& Stability
Output Freq
10.0 to 250MHz
Tape/
Reel
* See Ordering Information for details
Specifications
Parameter
Supply Voltage
1
Supply Current
Frequency
Frequency Tolerance
Industrial
Extended Commercial
Aging
Output Logic Levels
Output logic high
Output logic low
Pk to Pk Output Swing
Output Transition time
2
Rise Time
Fall Time
Startup Time
3
Output Duty Cycle
Input Logic Levels
Input logic high
Input logic low
Output Disable Time
Output Enable Time
Enable Pull-Up
Resistor
4
Period Jitter
Integrated Phase Noise
Notes:
1.
2.
3.
4.
Symbol
Vdd
I
DD
f
0
Condition
R
L
=50Ω
T=25°C
Single Frequency
Includes frequency
variations due to initial
tolerance, temperature and
power supply voltage
1 year @25°C
R
L
=50Ω
T=25°C
20%/80%
T=25°C
Min.
2.25
Typ.
Max.
3.6
60
250
±15,±25,±50
±15,±25,±50
±5
Unit
V
mA
MHz
10
40
Δf
Δf
V
OH
V
OL
t
R
t
F
t
SU
SYM
V
IH
V
IL
t
DA
t
EN
ppm
ppm
Volts
mV
ps
ms
%
Volts
ns
us
kΩ
ps
RMS
ps
RMS
0.725
-
675
250
-
0.1
10
45
0.75*V
DD
-
55
-
0.25* V
DD
100
5
33
4
J
CC
12kHz – 20MHz Band
100kHz – 20MHz Band
200kHz – 20MHz Band
<3
<1
<0.7
Pin 6 (Vdd) should filtered with 0.1uf capacitor
Output Waveform and Test Circuit figures below define these parameters
Output frequency to within 100ppm of final stable output frequency.
Output is enabled if pad is floated or connected to Vdd
DISCERA, Inc.
●
Phone: +1 (408) 432-8600
1961 Concourse Drive, Suite E,
●
Fax: +1 (408) 432-8609
San Jose, California
95131
●
Email: sales@discera.com
●
●
USA
www.discera.com
All Rights Reserved. No part of this document may be copied or reproduced in any form without the prior written permission of Discera, Inc. Discera Inc. may update or make
changes to the contents, products, programs or services described at any time without notice. This document neither states nor implies any kind of warranty, including, but not
limited to implied warranties of merchantability or fitness for a particular use.
Page 2 | 2010-3-16
DSC8124 Series
Output Waveform
2.5 to 3.3V
PureSilicon™ Programmable HCSL Oscillator
Typical DC Termination Scheme
Vdd
0.10uf
6
Rs= 0 ohm for Test
Rs
2
5
Rs
3
4
Rs serves to match trace
impedances. Depending
on board layout, the value
may be from 0 to 30 ohm
100 Ohms
50
50
Test Circuit
All Rights Reserved. No part of this document may be copied or reproduced in any form without the prior written permission of Discera, Inc. Discera Inc. may update or make
changes to the contents, products, programs or services described at any time without notice. This document neither states nor implies any kind of warranty, including, but not
limited to implied warranties of merchantability or fitness for a particular use.
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