NCP1615
High Voltage High
Efficiency Power Factor
Correction Controller
The NCP1615 is a high voltage PFC controller designed to drive
PFC boost stages based on an innovative Current Controlled
Frequency Foldback (CCFF) method. In this mode, the circuit
operates in critical conduction mode (CrM) when the inductor current
exceeds a programmable value. When the current is below this preset
level, the NCP1615 linearly decays the frequency down to a minimum
of about 26 kHz at the sinusoidal zero−crossing. CCFF maximizes the
efficiency at both nominal and light load. In particular, the standby
losses are reduced to a minimum. Innovative circuitry allows near−
unity power factor even when the switching frequency is reduced.
The integrated high voltage start−up circuit eliminates the need for
external start−up components and consumes negligible power during
normal operation. Housed in a SOIC−14 or SOIC−16 package, the
NCP1615 incorporates the features necessary for robust and compact
PFC stages, with few external components.
General Features
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16
1
SOIC−16 NB
CASE 752AC
14
1
SOIC−14 NB
CASE 751AN
MARKING DIAGRAMS
16
NCP1615xxG
AWLYWW
1
1
14
NCP1615xxG
AWLYWW
•
High Voltage Start−Up Circuit with Integrated Brownout Detection
•
Input to Force Controller into Standby Mode
•
Restart Pin Allows Adjustment of Bulk Voltage Hysteresis in
•
•
•
•
•
•
•
•
•
•
•
•
•
Standby Mode
Skip Mode Near the Line Zero Crossing
Fast Line / Load Transient Compensation
Valley Switching for Improved Efficiency
High Drive Capability: −500 mA/+800 mA
Wide V
CC
Range: from 9.5 V to 28 V
Input Voltage Range Detection
Input X2 Capacitor Discharge Circuitry
Power Saving Mode (PSM) Enables < 30 mW No−load
Power Consumption
This is a Pb and Halogen Free Device
NCP1615xx = Specific Device Code
xx
= A, A1, B, C, C2, C3, C4, C5, D or D2
A
= Assembly Location
WL
= Wafer Lot
Y
= Year
WW
= Work Week
G
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
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•
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•
Open Pin Protection for FB and FOVP/BUV Pins
Internal Thermal Shutdown
Bi−Level Latch Input for OVP and OTP
Bypass/Boost Diode Short Circuit Protection
Open Ground Pin Protection
Safety Features
Typical Applications
Adjustable Bulk Undervoltage Detection (BUV)
Soft Overvoltage Protection
Line Overvoltage Protection
Overcurrent Protection
HVFB
FB
Restart
FOVP/BUV
VControl
FFControl
Fault
STDBY
HV
PC Power Supplies
Off Line Appliances Requiring Power Factor Correction
LED Drivers
Flat TVs
FB
Restart
HV
VCC
DRV
GND
CS/ZCD
PFCOK
PIN CONNECTIONS
VCC
DRV
GND
CS/ZCD
PFCOK
PSTimer
FOVP/BUV
VControl
FFControl
Fault
STDBY
NCP1615 16 Pins (Top View)
NCP1615 14 Pins (Top View)
©
Semiconductor Components Industries, LLC, 2016
1
June, 2016 − Rev. 8
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Publication Order Number:
NCP1615/D
NCP1615
Dbypass
Lin
F1
L
BD1
L1
Lcm
RV1
CX1
BD2
BD3
Cin1
Cin2
Raux
Rsense
Rzcd
Daux
Rgs
L1 N1
Rhv1
Dhv1
Rcs
BD4
PFCok
Rhv2
Rfb2
Dhv2
U1
HVFB
FB
Restart
PFCok
CS/ZCD FOVP/BUV
STDBY
Fault
VCC
Control
FFcontrol
DRV
PStimer
GND
HV
Rrestart1
Rfovp/buv1
Standby
DRV
Cvcc
Ext. Vcc
Rpsm
Vaux
Rrestart2
Rfovp/buv2
Vaux
Lboost
Mboost
Rdrv
DRV
Rfb1
Dboost
Cbulk
N1
N
Rcomp1
Rfault
Ccomp1
Ccomp2
Rff
Cpsm
PSM_Control NCP1615C/D
Figure 1. NCP1615C/D Typical Application Circuit
Dbypass
Lin
F1
L
BD1
RX1
Lcm
RV1
CX1
RX2
N
BD4
N1
Cin2
Rzcd
BD2
BD3
Cin1
Raux
Rsense
L1
Daux
Rgs
L1 N1
Rhv1
Dhv1
Rcs
PFCok
Rhv2
Dhv2
U1
FB
Restart
PFCok FOVP/BUV
CS/ZCD STDBY
Fault
VCC
DRV
Control
GND
FFcontrol
HV
NCP1615A/B
Ccomp2
Rff
Rfb2
Rrestart1
Rfovp/buv1
Standby
Rrestart2
DRV
Cvcc
Rfovp/buv2
Vaux
Lboost
Mboost
Rdrv
DRV
Rfb1
Dboost
Cbulk
Rcomp1
Rfault
Ccomp1
Ext. Vcc
Vaux
Figure 2. NCP1615A/B Typical Application Circuit
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NCP1615
Enable PFC
HVFB
Line OVP
Blank Delay
UVP1
SoftOVP
DRE
In_Regulation
I
boost(DRE)
V
DD
DRE
I
FB(bias)
FB
V
DD
Line_OVP
FB Logic
Line Removal Line Removal
Detector
BO_NOK
Brownout
Detector
LLine
Thermal
Line Sense
Shutdown
Detector
I
SENSE
VREF
VDD
IREF
HV
Istart2
I
boost(startup)
V
REF
Error
Amplifier
V
DD
Upper
Clamp
Lower
Clamp
BO
OCP
staticOVP
OverStress
Line_OVP
Standby
Regulator
I
CC(discharge)
Istart1
VCC
CENTRAL
LOGIC
V
CC(reset)
V
CC(on)
/V
CC(off)
Control
StaticOVP
Level
Shift
DT
Restart_OK
SKIP
Standby
softOVP
LLine
I
Control(BO)
OFF
V
FOVP
V
BUV
V
REGUL
UVP1
Latch
Vton OFF
Vton
Processing
Circuitry
Internal
Timing
Ramp
DRV
V
REGUL
V
UVP2
I
FOVP/UVP(bias)
V
UVP3
V
restart
FOVP/
BUV
Auto−Recovery
PWM
PWM
Comparator
PFC_OK
Restart_OK
Restart
I
Restart(bias)
V
CC
Clamp
CLK
Enable PFC
STDWN
PFC_OK Clear
Vton OFF
OFF
BO
STOP
PWM
STOP
V
DD
I
PSTimer2
I
PSTimer1
S
R
Standby
Q
DRV
GND
I
SENSE
FFcontrol
OverStress
DT
CLK
SKIP
In PSM
Current Information
Generator and
dead−time control
LLline
PFCok
Driver
DRV
ZCD
−
+
V
DD
STDBY
V
standby
In PSM
V
PSTimer2
Q
S
R
In_Regulation
In PSM
Power
Saving
Mode (PSM)
Detector
DRV
Blanking
Delay
OCP
OverStress
Detection
of excessive
current
Latch
ZCD
Auto−Recovery
Control
Auto−Recovery
Version B/D
In PSM
PStimer
PFCok
PFC_OK
PFC_OK Clear
I
CS/ZCD2
V
DD
I
Fault
Fault
R
Fault(clamp)
OVP
Comparator
+
−
Current Limit
Comparator
DRV
LEB
t
off1
I
CS/ZCD1
V
PS_in
/
V
PS_out
V
DD
V
DD
CS/ZCD
OTP Comparator
Blanking
Delay
V
Fault(clamp)
t
delay(OTP)
+
Enable PFC
V
Fault(OTP)
Delay
−
t
blank(OTP)
Version A/B
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−
+
t
delay(OVP)
t
OCP(LEB)
V
OCP
DRV
LEB
t
OVS(LEB)
V
ZCD(rising)
/
V
ZCD(falling)
V
Fault(OVP)
+
−
ZCD
Comparator
Version C/D
Version A/C
Figure 3. NCP1615 Functional Block Diagram
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NCP1615
Table 1. PIN FUNCTION DESCRIPTION
Pin Number
NCP1615C/D
1
NCP1615A/B
N/A
Name
HVFB
Function
High voltage PFC feedback input. An external resistor divider is used to sense the
PFC bulk voltage. The divider high side resistor chain from the PFC bulk voltage
connects to this pin. An internal high−voltage switch disconnects the high side
resistor chain from the low side resistor when the PFC is latched or in PSM in
order to reduce input power.
This pin receives a portion of the PFC output voltage for the regulation and the
dynamic response enhancer (DRE) that speeds up the loop response when the
output voltage drops below 95.5% of the regulation level. V
FB
is also the input
signal for the Soft−Overvoltage Comparators as well as the Undervoltage (UVP)
Comparator. The UVP Comparator prevents operation as long as V
FB
is lower
than 12% of the reference voltage (V
REF
). The Soft−Overvoltage Comparator
(Soft−OVP) gradually reduces the duty ratio to zero when V
FB
exceeds 105% of
V
REF
. A 250 nA sink current is built−in to trigger the UVP protection and disable
the part if the feedback pin is accidentally open. A dedicated comparator monitors
the bulk voltage and disables the controller if a line overvoltage fault is detected.
This pin receives a portion of the PFC output voltage for determining the restart
level after entering standby mode.
Input terminal for the Fast Overvoltage (Fast−OVP) and Bulk Undervoltage (BUV)
Comparators. The circuit disables the driver if the V
FOVP/BUV
exceeds the V
FOVP
threshold which is set 2% higher than the reference for the Soft−OVP comparator
monitoring the FB pin. This allows the both pins to receive the same portion of the
output voltage. The BUV Comparator trips when V
FOVP/BUV
falls below 76% of the
reference voltage. A BUV fault disables the driver and grounds the PFCOK pin.
The BUV function has no action whenever the PFCOK pin is in low state. Once
the downstream converter is enabled the BUV Comparator monitors the output
voltage to ensure it is high enough for proper operation of the downstream con-
verter. A 250 nA current pulls down the pin and disable the controller if the pin is
accidentally open.
The error amplifier output is available on this pin. The network connected between
this pin and ground sets the regulation loop bandwidth. It is typically set below 20
Hz to achieve high power factor ratios. This pin is grounded when the controller is
disabled. The voltage on this pin gradually increases during power up to achieve a
soft−start.
This pin sources a current representative to the line current. Connect a resistor
between this pin and GND to generate a voltage representative of the line current.
When this voltage exceeds the internal 2.5 V reference, the circuit operates in
critical conduction mode. If the pin voltage is below 2.5 V, a dead−time is gen-
erated that approximately equates [83
ms
•
(1 − (V
FFcontrol
/V
REF
))]. By this means,
the circuit increases the deadtime when the current is smaller and decreases the
deadtime as the current increases.
The circuit skips cycles whenever V
FFcontrol
is below 0.65 V to prevent the PFC
stage from operating near the line zero crossing where the power transfer is par-
ticularly inefficient. This does result in a slightly increased distortion of the current.
If superior power factor is required, offset the voltage on this pin by more than
0.75 V to inhibit skip operation.
The controller enters fault mode if the voltage of this pin is pulled above or below
the fault thresholds. A precise pull up current source allows direct interface with an
NTC thermistor. Fault detection triggers a latch or auto−recovery depending on
device version.
This pin is used to force the controller into standby mode.
Power saving mode (PSM) timer adjust. A capacitor between this pin and GND,
C
PSTimer
, sets the delay time before the controller enters power saving mode.
Once the controller enters power saving mode the IC is disabled and the current
consumption is reduced to a maximum of 100
mA.
The input filter capacitor dis-
charge function is available while in power saving mode. The device enters PSM if
the voltage on this pin exceeds the PSM threshold, V
PS_in
. A secondary side con-
troller optocoupler pulls down on the pin to prevent the controller from entering
PSM when the load is connected to the power supply. The controller is enabled
once V
PSTimer
drops below V
PS_out
.
This pin is grounded until the PFC output has reached its nominal level. It is also
grounded if the controller detects a fault. The voltage on this pin is 5 V once the
controller reaches regulation.
2
1
FB
3
4
2
3
Restart
FOVP/BUV
5
4
Control
6
5
FFcontrol
7
6
Fault
8
9
7
N/A
STDBY
PSTimer
10
8
PFCOK
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NCP1615
Table 1. PIN FUNCTION DESCRIPTION
Pin Number
NCP1615C/D
11
NCP1615A/B
9
Name
CS/ZCD
Function
This pin monitors the MOSFET current to limit its maximum current. This pin is
also connected to an internal comparator for zero current detection (ZCD). This
comparator is designed to monitor a signal from an auxiliary winding and to detect
the core reset when this voltage drops to zero. The auxiliary winding voltage is to
be applied through a diode to avoid altering the current sense information for the
on time (see application schematic).
Ground reference.
MOSFET driver. The high current capability of the totem pole gate drive (−0.5/
+0.8 A) makes it suitable to effectively drive high gate charge power MOSFETs.
Supply input. This pin is the positive supply of the IC. The circuit starts to operate
when V
CC
exceeds V
CC(on)
. After start−up, the operating range is 9.5 V up to 28 V.
Removed for creepage distance.
HV
This pin is the input for the line removal detection, line level detection, and
brownout detection circuits. For versions C and D, this pin is also the input for the
high voltage start−up circuit.
12
13
14
15
16
10
11
12
13
14
GND
DRV
VCC
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