EEWORLDEEWORLDEEWORLD

Part Number

Search

54102-G46-50

Description
Board Connector, 100 Contact(s), 2 Row(s), Male, Straight, 0.1 inch Pitch, Solder Terminal, Black Insulator, Receptacle
CategoryThe connector    The connector   
File Size161KB,1 Pages
ManufacturerAmphenol
Websitehttp://www.amphenol.com/
Download Datasheet Parametric View All

54102-G46-50 Overview

Board Connector, 100 Contact(s), 2 Row(s), Male, Straight, 0.1 inch Pitch, Solder Terminal, Black Insulator, Receptacle

54102-G46-50 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerAmphenol
Reach Compliance Codeunknown
ECCN codeEAR99
Other featuresPOLY BAG PACKAGING
body width0.19 inch
subject depth0.1 inch
body length5 inch
Body/casing typeRECEPTACLE
Connector typeBOARD CONNECTOR
Contact to complete cooperationAU ON NI
Contact completed and terminatedTin/Lead (Sn/Pb) - with Nickel (Ni) barrier
Contact point genderMALE
Contact materialPHOSPHOR BRONZE
contact modeRECTANGULAR
Contact styleSQ PIN-SKT
Dielectric withstand voltage1500VAC V
Insulation resistance5000000000 Ω
Insulator colorBLACK
insulator materialTHERMOPLASTIC
JESD-609 codee0
Manufacturer's serial number54102
Plug contact pitch0.1 inch
Match contact row spacing0.1 inch
Installation methodSTRAIGHT
Installation typeBOARD
Number of connectorsONE
PCB row number2
Number of rows loaded2
Maximum operating temperature130 °C
Minimum operating temperature-65 °C
PCB contact patternRECTANGULAR
PCB contact row spacing2.54 mm
Plating thickness30u inch
Rated current (signal)3 A
GuidelineUL, CSA
reliabilityCOMMERCIAL
Terminal length0.11 inch
Terminal pitch2.54 mm
Termination typeSOLDER
Total number of contacts100
PDM: Rev:F
STATUS:
Released
Printed: Aug 02, 2002
Is there any FPGA chip with built-in CAN protocol?
I'd like to ask you guys, are there any FPGA chips with built-in CAN protocol? If not, I want to use Verilog language to implement CAN controller module, do you have any suitable materials to recommen...
大萝卜的小蝌蚪 FPGA/CPLD
Debugging issues with sdram in NIOS II
I used SDRAM in NIOS II, but the following prompt appeared during the simulation: Error! : Failed memory access in component cpu - Unable to write data 0x18 to in valid memory address 0x1800000 Error!...
亭哥V5 FPGA/CPLD
Reminder for short message replies to old posts...
Every time I log in, I get a short message reminder. . . At first glance, they are all replies to old posts, such as posts from one or two years ago. . .After reading the function description of the f...
open82977352 Suggestions & Announcements
TTL
Why is the source current ×6 and the sink current ×3?...
初学00000001 Analog electronics
MSP430F149 MCU header file
#define TACCR1_ 0x0174 /* Timer A capture/compare register 1 */ sfrw TACCR1 = TACCR1_; What does sfrw mean in the above two lines of code? thanks....
zhengrs Embedded System
Calculation of Equivalent Capacitance of Capacitance Multiplier
To design a power supply, I remembered the post marked earlier - [url=https://www.amobbs.com/thread-4710474-1-1.html]Ultra-low ripple linear regulated power supply circuit[/url], which mentioned the c...
Tobey Power technology

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 950  80  618  784  1284  20  2  13  16  26 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号