EEWORLDEEWORLDEEWORLD

Part Number

Search

54122-418-05-2050

Description
Board Connector, 10 Contact(s), 2 Row(s), Male, Straight, 0.1 inch Pitch, Solder Terminal, Locking, Black Insulator, Receptacle
CategoryThe connector    The connector   
File Size107KB,1 Pages
ManufacturerAmphenol
Websitehttp://www.amphenol.com/
Download Datasheet Parametric View All

54122-418-05-2050 Overview

Board Connector, 10 Contact(s), 2 Row(s), Male, Straight, 0.1 inch Pitch, Solder Terminal, Locking, Black Insulator, Receptacle

54122-418-05-2050 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerAmphenol
Reach Compliance Codecompliant
ECCN codeEAR99
body width0.19 inch
subject depth0.807 inch
body length0.5 inch
Body/casing typeRECEPTACLE
Connector typeBOARD CONNECTOR
Contact to complete cooperationSN ON NI
Contact completed and terminatedTin/Lead (Sn/Pb) - with Nickel (Ni) barrier
Contact point genderMALE
Contact materialPHOSPHOR BRONZE
contact modeRECTANGULAR
Contact styleSQ PIN-SKT
Insulation resistance5000000000 Ω
Insulator colorBLACK
insulator materialTHERMOPLASTIC
JESD-609 codee0
Manufacturer's serial number54122
Plug contact pitch0.1 inch
Match contact row spacing0.1 inch
Installation option 1LOCKING
Installation methodSTRAIGHT
Installation typeBOARD
Number of connectorsONE
PCB row number2
Number of rows loaded2
Maximum operating temperature125 °C
Minimum operating temperature-65 °C
PCB contact patternRECTANGULAR
PCB contact row spacing2.54 mm
Plating thickness79u inch
Rated current (signal)3 A
GuidelineUL, CSA
reliabilityCOMMERCIAL
Terminal length0.12 inch
Terminal pitch2.54 mm
Termination typeSOLDER
Total number of contacts10
PDM: Rev:K
STATUS:
Released
Printed: Mar 10, 2011
.
FPGA Design Practice (Logic)
FPGA Design Practice (Logic) is aimed at the vast number of FPGA/CPLD beginners. It explains FPGA/CPLD and related basic knowledge from scratch, and uses a motherboard-based learning kit that supports...
arui1999 Download Centre
SIMterix-Simplies~4~ Verilog
In the case of mixed integer and analog systems, simulation can only simulate Verilog or analog. If the digital part has only output, it is OK, just edit the voltage source and import the waveform fil...
xutong Analog electronics
CCS Error
DEBUG: Error 2863: The control PushButton2 on dialog Installation_Type_Dialog needs the icon TypicalInstall.bmp in size 48x48, but that size is not available. Loading the first available sizeInternal ...
feiyun DSP and ARM Processors
When the CEdit control is deleted by pressing the back key under EVC4.0\wince5, the content of CEdit is not updated
The cursor has moved over, but the string is still displayed there. It is updated only when the line is deleted. If you enter again, it will overlap with the previous word. And this problem only occur...
zhangheng Embedded System
After IAR compiles and downloads the code, how do I know the total length of the code and where the address is from and to?
Is there any automatically generated file that I can look at directly?Thanks!...
jsglf Microcontroller MCU
Is it possible to add a count loop in the combinational logic of a three-stage state machine?
Assuming the clock cycle is 40ns, the state changes of my sequential circuit are about 80ns, 160ns, 160ns, 40ns. In a state, it relies on counting loops to stay in this state until the loop count meet...
lvben5d FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2129  1977  663  2449  957  43  40  14  50  20 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号